Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
FEATURES
•
8-bit bidirectional I/O port with handshake
•
Register status flag flip-flops
•
Separate clock enable and output enable
•
Parity generation and parity check
•
B outputs and parity output sink 64mA
DESCRIPTION
The 74F522 Octal Registered Transceiver contains two 8-bit
registers for temporary storage of data flowing in either direction.
Each register has its own clock (CPR, CPS) and Clock Enable
(CER, CES) inputs, as well as a flag flip-flop that is set automatically
as the register is loaded. The flag output will be reset when the
Output Enable returns to High after reading the output port. Each
register has a separate Output Enable (OEAS, OEBR) for its 3-State
buffer. The separate Clocks, Flags and Enables provide
considerable flexibility as I/O ports for demand-response data
transfer. When data is transferred from the A port to the B port, a
parity bit is generated. On the other hand, when data is transferred
from the B port to the A port, the parity of input data on B0–B7 is
checked.
TYPICAL SUPPLY
CURRENT
(TOTAL)
120mA
PIN CONFIGURATION
B4 1
B5
B6
B7
OEBR
CPR
CER
V
CC
ERROR
2
3
4
5
6
7
8
9
28 B3
27 B2
26 B1
25 B0
24 FR
23 PARITY
22 GND
21 CES
20 CPS
19 OEAS
18 A0
17 A1
16 A2
15 A3
FS 10
A7 11
A6 12
A5 13
A4 14
SF01039
LOGIC SYMBOL (IEEE/IEC)
XCVR
6
7
5
20
21
19
1C2
EN1’
EN6
6C4
EN3
EN6
Z7
6
6,7
5
9
10
14
5,6
5,6
23
TYPE
74F552
TYPICAL f
MAX
85MHz
ORDERING INFORMATION
DESCRIPTION
28-Pin Plastic DIP
(600mil)
28-Pin Plastic SOL
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F552N
N74F552D
18
3,4,6
1,2,6
25
26
27
28
1
2
3
4
PKG DWG #
17
SOT117-2
SOT136-1
16
15
14
13
12
LOGIC SYMBOL
18
17 16
15
14
13
12
11
11
A0
6
7
21
20
19
5
CPR
CER
CES
CPS
OEAS
OEBR
B0 B1
B2
B3
B4
B5
PARITY
FS
FR
ERROR
23
10
24
9
A1 A2
A3
A4
A5
A6
A7
SF01040
B6
B7
V
CC
= Pin 8
GND = Pin 22
25
26
27
28
1
2
3
4
SF01041
1991 Jan 02
2
853–1098 01347
Philips Semiconductors
Product specification
Octal registered transceiver with parity and flags (3-State)
74F552
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
A0–A7
B0–B7
CPR
CPS
CER
CES
OEBR
OEAS
A Data inputs
B Data inputs
R registers clock input (active rising edge)
S registers clock input (active rising edge)
R registers clock Enable input (active Low)
S registers clock Enable input (active Low)
A-to-B Output Enable input (active Low)
and clear FS output (active Low)
B-to-A Output Enable input (active Low)
and clear FR output (active Low)
Parity bit transceiver input
PARITY
Parity bit transceiver output
ERROR
A0–A7
B0–B7
FR
FS
Parity check output (active Low)
A Data outputs
B Data outputs
A-to-B Status Flag output (active High)
B-to-A Status Flag output (active High)
750/106.7
50/33.3
150/40
750/106.7
50/33.3
50/33.3
15mA/64mA
1.0mA/20mA
3.0mA/24mA
15mA/64mA
1.0mA/20mA
1.0mA/20mA
DESCRIPTION
74F(U.L.)
HIGH/LOW
3.5/1.0
3.5/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/2.0
3.5/1.0
LOAD VALUE
HIGH/LOW
70µA/0.6mA
70µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/1.2mA
20µA/1.2mA
70µA/0.6mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
FUNCTIONAL DESCRIPTION
Data applied to the A inputs are entered and stored on the rising
edge of the CPR clock pulse, provided that the CER is Low;
simultaneously, the status flip-flop is set and the A-to-B flag (FR)
output goes High. As the CER returns to High, the data will be held
in R register. This data entered from the A inputs will appear at the B
port I/O pins after the OEBR has gone Low. When OEBR is Low, a
parity bit appears at the PARITY pin, which will be set High when
there is an even number of 1s or all 0s at the Q outputs of the R
register. After the data is assimilated, the receiving system clears
the flag FR, by changing the signal at the OEBR pin from Low to
High. Data flow from B-to-A proceeds in the same manner described
for A-to-B flow. A Low at the CES pin and a Low-to-High transition at
the CPS pin enters the B input data and the parity input data into the
S register and the parity register respectively and set the flag output
FS to High. A Low signal at the OEAS pin enables the A port I/O
pins and a Low-to-High transition of the OEAS signal clears the FS
flag. When OEAS is Low, the parity check output ERROR will be
High if there is an odd number of 1s at the Q outputs of the S
register and the parity register.
R or S REGISTER FUNCTION TABLE
INPUTS
An or Bn
X
L
H
H =
L =
NC=
X =
X
=
↑
=
↑
=
CPX
X
↑
↑
CEX
H
L
L
OUTPUTS
INTERNAL Q
NC
L
H
NC
OPERATING
MODE
Hold data
Load data
Keep old data
X
↑
L
High voltage level
Low voltage level
No change
Don’t care
R
or
S
for
CPX
and
CEX
Low-to-High transition
Not Low-to-High transition
OUTPUT CONTROL TABLE
INPUT
OEXX
H
OUTPUTS
INTERNAL Q
X
An or Bn
Z
L
H
OPERATING
MODE
Disable outputs
Enable outpus
H =
L =
X =
XX=
Z =
L
L
L
H
High voltage level
Low voltage level
Don’t care
AS
or
BR
High impedance “off” state
1991 Jan 02
3
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