MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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HDTMOS E-FET
™
High Density Power FET
DPAK for Surface Mount
N–Channel Enhancement Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters, and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
•
Avalanche Energy Specified
•
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
•
Diode Is Characterized for Use In Bridge Circuits
•
IDSS and VDS(on) Specified at Elevated Temperature
•
Surface Mount Package Available in 16 mm, 13″ / 2500 Unit
Tape & Reel, Add “T4” Suffix to Part Number
MTD1302
TMOS POWER FET
20 AMPERES
30 VOLTS
RDS(on) = 0.022 OHM
™
CASE 369A–13, Style 2
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp
≤
10 ms)
Drain Current — Continuous
Drain Current
— Continuous @ 100°C
Drain Current
— Single Pulse (tp
≤
10
µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25
Ω)
Thermal Resistance
Junction to Case
Junction–to–Ambient
Junction–to–Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5.0 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
30
30
±
20
±
20
20
16
60
74
0.592
1.75
– 55 to 150
200
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
°C/W
TJ, Tstg
EAS
R
θJC
R
θJA
R
θJA
TL
1.67
100
71.4
260
°C
HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
©
Motorola, Inc. 1997
Motorola TMOS Power MOSFET Transistor Device Data
1
MTD1302
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current
(VGS =
±
20 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 10 Adc)
(VGS = 4.5 Vdc, ID = 5.0 Adc)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C)
Forward Transconductance
(VDS = 10 Vdc, ID = 10 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(VDS = 24 Vd , ID = 20 Adc,
Vdc,
Ad ,
(
VGS = 5.0 Vdc)
Vdc,
(VDD = 15 Vd ID = 20 Adc,
Ad
VGS = 10 Vdc
Vdc,
RG = 9.1
Ω)
)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
Gate Charge
(
(VDS = 24 Vd , ID = 20 Adc,
Vdc,
Ad ,
VGS = 10 Vdc)
QT
Q1
Q2
Q3
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 20 Adc, VGS = 0 Vdc)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(
(IS = 20 Adc, VGS = 0 Vdc,
Ad ,
Vd ,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
(1) Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
trr
ta
tb
QRR
VSD
—
—
—
—
—
—
0.83
0.79
38
19
20
36
1.1
—
—
—
—
—
µC
ns
Vdc
—
—
—
—
—
—
—
—
—
—
—
—
7.2
52
45
73
14.5
2.2
8.8
6.8
27
2.2
10
7.2
15
104
90
146
21.8
—
—
—
40.5
—
—
—
nC
nC
ns
(VDS = 25 Vdc, VGS = 0 Vdc,
Vdc
Vdc
f = 1.0 MHz)
Ciss
Coss
Crss
—
—
—
755
370
102
1162
518
204
pF
VGS(th)
1.0
RDS(on)
—
—
VDS(on)
—
—
gFS
10
16
—
0.38
—
0.5
0.33
Mhos
0.019
0.026
0.022
0.029
Vdc
1.5
2.0
Ohms
Vdc
V(BR)DSS
30
IDSS
—
—
IGSS
—
—
100
—
—
10
100
nAdc
—
—
µAdc
Vdc
Symbol
Min
Typ
Max
Unit
2
Motorola TMOS Power MOSFET Transistor Device Data
MTD1302
TYPICAL ELECTRICAL CHARACTERISTICS
40
10 V
35
ID, DRAIN CURRENT (AMPS)
30
25
20
15
10
5.0
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS = 3.0 V
TJ = 25°C
5.0 V
4.0 V
25
ID, DRAIN CURRENT (AMPS)
VDS
≥
10 V
20
15
10
TJ = 125°C
5.0
– 55°C
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
25°C
30
Figure 1. On–Region Characteristics
R DS(on), DRAIN–TO–SOURCE ON–RESISTANCE (OHMS)
RDS(on), DRAIN–TO–SOURCE ON–RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.03
VGS = 10 V
TJ = 100°C
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
10
15
20
25
30
35
40
ID, DRAIN CURRENT (AMPS)
10 V
TJ = 25°C
VGS = 4.5 V
0.02
25°C
– 55°C
0.01
10
15
20
25
30
35
40
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus
Drain Current and Temperature
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
3.0
ID = 10 A
1000
2.0
IDSS, LEAKAGE (nA)
100
TJ = 125°C
100°C
10
VGS = 10 V
1.0
25°C
1.0
0
–50
–25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
0.1
5.0
10
15
20
25
30
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTD1302
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
2500
Ciss
2000
C, CAPACITANCE (pF)
1500
Crss
Ciss
Coss
VDS = 0 V VGS = 0 V
–5.0
5.0
0
VGS
VDS
Crss
10
15
20
25
1000
500
0
–10
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
MTD1302
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
14
12
QT
10
8.0
6.0
Q1
4.0
2.0
0
Q3
VDS
Q2
ID = 20 A
TJ = 25°C
6.0
3.0
VGS
9.0
18
15
12
1000
VDD = 15 V
ID = 20 A
VGS = 10 V
TJ = 25°C
tf
tr
td(off)
10
td(on)
100
t, TIME (ns)
1.0
1.0
0
0 2.0 4.0 6.0 8.0 10 12 14 16 18 20 22 24 26 28 30
QG, TOTAL GATE CHARGE (nC)
10
RG, GATE RESISTANCE (OHMS)
100
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de-
vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
20
18
I S , SOURCE CURRENT (AMPS)
16
14
12
10
8.0
6.0
4.0
2.0
0
0.40 0.45 0.50 0.55 0.60
0.65 0.70 0.75
0.80 0.85 0.90
TJ = 25°C
di/dts. The diode’s negative di/dt during ta is directly con-
trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac-
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re-
covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen-
erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
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