MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTW32N20E/D
™
Data Sheet
TMOS E-FET.
™
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
Designer's
MTW32N20E
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
•
Avalanche Energy Specified
•
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
IDSS and VDS(on) Specified at Elevated Temperature
•
Isolated Mounting Hole
TMOS POWER FET
32 AMPERES
200 VOLTS
RDS(on) = 0.075 OHM
®
D
G
S
CASE 340K–01, Style 1
TO–247AE
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage — Continuous
Drain Current — Continuous
Drain Current
— Continuous @ 100°C
Drain Current
— Single Pulse (tp
≤
10
µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vpk, IL = 32 Apk, L = 1.58 mH, RG = 25
Ω
)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
EAS
R
θJC
R
θJA
TL
Value
200
200
±
20
32
19
128
180
1.44
– 55 to 150
810
0.7
40
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/°C
°C
mJ
°C/W
°C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Sil Pad is a trademark of the Bergquist Company
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
©
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1996
1
MTW32N20E
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 V, ID = 250
µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 200 Vdc, VGS = 0)
(VDS = 200 Vdc, VGS = 0, TJ = 125°C)
Gate–Body Leakage Current (VGS =
±
20 Vdc, VDS = 0)
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250
µAdc)
Temperature Coefficient (Negative)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 16 Adc)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 32 Adc)
(ID = 16 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 16 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS*
¦
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
Vd ,
Ad ,
(
(VDS = 160 Vdc, ID = 32 Adc,
VGS = 10 Vdc)
Vdc,
Adc,
(VDD = 100 Vd ID = 32 Ad
VGS = 10 Vdc
Vdc,
RG = 6.2
Ω)
)
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
(IS = 32 Adc, VGS = 0)
(IS = 16 Adc, VGS = 0, TJ = 125°C)
VSD
—
—
trr
(
(IS = 32 Adc, VGS = 0,
Ad ,
0,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
* Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
¦
Switching characteristics are independent of operating junction temperature.
LD
LS
—
—
5.0
13
—
—
nH
nH
ta
tb
QRR
—
—
—
—
1.1
0.9
280
195
85
2.94
2.0
—
—
—
—
—
µC
ns
Vdc
—
—
—
—
—
—
—
—
25
120
75
91
85
12
40
30
50
240
150
182
120
—
—
—
nC
ns
(VDS = 25 Vdc, VGS = 0,
Vdc
0
f = 1.0 MHz)
Ciss
Coss
Crss
—
—
—
3600
130
690
5000
250
1000
pF
VGS(th)
2.0
—
RDS(on)
VDS(on)
—
—
gFS
12
—
—
—
3.0
2.7
—
mhos
—
—
8.0
0.064
4.0
—
0.075
Vdc
mV/°C
Ohm
Vdc
V(BR)DSS
200
—
IDSS
—
—
IGSS
—
—
—
—
250
1000
100
nAdc
—
247
—
—
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
2
Motorola TMOS Power MOSFET Transistor Device Data
MTW32N20E
YPICAL ELECTRICAL CHARACTERISTICS
100
TJ = 25°C
I D , DRAIN CURRENT (AMPS)
80
8V
60
7V
40
6V
20
5V
0
0
2
4
6
8
10
0
0
2
4
6
8
10
VGS = 10 V
9V
I D , DRAIN CURRENT (AMPS)
40
VDS
≥
10 V
50
TJ = – 55°C
100°C
25°C
30
20
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.16
VGS = 10 V
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
0
8
16
24
32
40
48
56
64
– 55°C
25°C
TJ = 100°C
0.1
TJ = 25°C
0.09
0.08
VGS = 10 V
0.07
15 V
0.06
0.05
0
8
16
24
32
40
48
56
64
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
2.5
VGS = 10 V
ID = 16 A
10000
VGS = 0 V
I DSS, LEAKAGE (mA)
2000
1000
TJ = 125°C
2
1.5
200
100
100°C
20
25°C
0
50
100
150
200
1
0.5
–50
–25
0
25
50
75
100
125
150
10
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTW32N20E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies great-
ly with applied voltage. Accordingly, gate charge data is used.
In most cases, a satisfactory estimate of average input current
(IG(AV)) can be made from a rudimentary analysis of the drive
circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive
load, VGS remains virtually constant at a level known as the
plateau voltage, VSGP. Therefore, rise and fall times may be
approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is not
constant. The simplest calculation uses appropriate values
from the capacitance curves in a standard equation for voltage
change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
10000
VDS = 0
The capacitance (Ciss) is read from the capacitance curve at a
voltage corresponding to the off–state condition when calcu-
lating td(on) and is read at a voltage corresponding to the on–
state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by L di/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
VGS = 0
TJ = 25°C
8000
C, CAPACITANCE (pF)
Crss
6000
4000
Ciss
2000
Coss
0
10
5
VGS
0
VDS
5
10
15
20
25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4
Motorola TMOS Power MOSFET Transistor Device Data
MTW32N20E
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
20
TJ = 25°C
ID = 32 A
VDS = 160 V
200
180
160
140
QT
Q2
120
100
80
VGS
60
40
Q3
0
10
20
30
40
50
60
70
QT, TOTAL CHARGE (nC)
80
90
20
0
100
1000
TJ = 25°C
ID = 32 A
VDD = 100 V
VGS = 10 V
td(off)
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
tr
tf
16
VDS
200
t, TIME (ns)
100
td(on)
12
8
Q1
4
20
10
2
1
1
2
10
20
RG, GATE RESISTANCE (OHMS)
100
0
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
30
I S , SOURCE CURRENT (AMPS)
TJ = 25°C
VGS = 0 V
20
10
0
0
0.2
0.4
0.6
0.8
1
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain–to–source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction tem-
perature and a case temperature (TC) of 25°C. Peak repetitive
pulsed power limits are determined by using the thermal re-
sponse data in conjunction with the procedures discussed in
AN569, “Transient Thermal Resistance–General Data and Its
Use.”
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10µs. In addition the total power averaged
over a complete switching cycle must not exceed (TJ(MAX) –
TC)/(R
θJC
).
A Power MOSFET designated E–FET can be safely used in
switching circuits with unclamped inductive loads. For reliable
operation, the stored energy from circuit inductance dissi-
pated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases non–linearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
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