MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by BCP56T1/D
NPN Silicon
Epitaxial Transistor
These NPN Silicon Epitaxial transistors are designed for use in audio amplifier
applications. The device is housed in the SOT-223 package, which is designed for
medium power surface mount applications.
•
High Current: 1.0 Amp
•
The SOT-223 package can be soldered using wave or reflow. The formed leads
absorb thermal stress during soldering, eliminating the possibility of damage to
the die
•
Available in 12 mm Tape and Reel
Use BCP56T1 to order the 7 inch/1000 unit reel
Use BCP56T3 to order the 13 inch/4000 unit reel
•
PNP Complement is BCP53T1
COLLECTOR 2,4
BCP56T1
SERIES
Motorola Preferred Device
MEDIUM POWER
NPN SILICON
HIGH CURRENT
TRANSISTOR
SURFACE MOUNT
4
BASE
1
EMITTER 3
1
2
3
CASE 318E-04, STYLE 1
TO-261AA
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Collector-Emitter Voltage
Collector-Base Voltage
Emitter-Base Voltage
Collector Current
Total Power Dissipation @ TA = 25°C(1)
Derate above 25°C
Operating and Storage Temperature Range
Symbol
VCEO
VCBO
VEBO
IC
PD
TJ, Tstg
Value
80
100
5
1
1.5
12
– 65 to 150
Unit
Vdc
Vdc
Vdc
Adc
Watts
mW/°C
°C
DEVICE MARKING
BCP56T1 = BH
BCP56-10T1 = BK
BCP56-16T1 = BL
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Junction-to-Ambient (surface mounted)
Maximum Temperature for Soldering Purposes
Time in Solder Bath
Symbol
R
θJA
TL
Max
83.3
260
10
Unit
°C/W
°C
Sec
1. Device mounted on a FR-4 glass epoxy printed circuit board 1.575 in. x 1.575 in. x 0.0625 in.; mounting pad for the collector lead = 0.93 sq. in.
Thermal Clad is a trademark of the Bergquist Company
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 1
Motorola Small–Signal
©
Motorola, Inc. 1996
Transistors, FETs and Diodes Device Data
1
BCP56T1 SERIES
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Characteristics
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector-Base Breakdown Voltage
(IC = 100
µAdc,
IE = 0)
Collector-Emitter Breakdown Voltage
(IC = 1.0 mAdc, IB = 0)
Emitter-Base Breakdown Voltage
(IE = 10
µAdc,
IC = 0)
Collector-Base Cutoff Current
(VCB = 30 Vdc, IE = 0)
Emitter-Base Cutoff Current
(VEB = 5.0 Vdc, IC = 0)
V(BR)CBO
V(BR)CEO
V(BR)EBO
ICBO
IEBO
100
80
5.0
—
—
—
—
—
—
—
—
—
—
100
10
Vdc
Vdc
Vdc
nAdc
µAdc
ON CHARACTERISTICS (2)
DC Current Gain
(IC = 5.0 mA, VCE = 2.0 V)
(IC = 150 mA, VCE = 2.0 V)
hFE
All Part Types
BCP56T1
BCP56-10T1
BCP56-16T1
All Types
VCE(sat)
VBE(on)
25
40
63
100
25
—
—
—
—
—
—
—
—
—
—
250
160
250
—
0.5
1.0
Vdc
Vdc
—
(IC = 500 mA, VCE = 2.0 V)
Collector-Emitter Saturation Voltage
(IC = 500 mAdc, IB = 50 mAdc)
Base-Emitter On Voltage
(IC = 500 mAdc, VCE = 2.0 Vdc)
DYNAMIC CHARACTERISTICS
Current-Gain — Bandwidth Product
(IC = 10 mAdc, VCE = 5.0 Vdc, f = 35 MHz)
2. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2.0%
fT
—
130
—
MHz
2
Motorola Small–Signal Transistors, FETs and Diodes Device Data
BCP56T1 SERIES
TYPICAL ELECTRICAL CHARACTERISTICS
1000
hFE, DC CURRENT GAIN
TJ = 125°C
TJ = 25°C
100
TJ = – 55°C
10
1
10
IC, COLLECTOR CURRENT (mA)
100
1000
Figure 1. DC Current Gain
f T, CURRENT-GAIN — BANDWIDTH PRODUCT (MHz)
1000
80
60
TJ = 25°C
C, CAPACITANCE (pF)
40
Cibo
100
20
10
8.0
6.0
Cobo
0.2
0.5
1.0 2.0
5.0 10
20
VR, REVERSE VOLTAGE (VOLTS)
50
100
10
1.0
10
100
IC, COLLECTOR CURRENT (mA)
1000
4.0
0.1
Figure 2. Current-Gain — Bandwidth Product
Figure 3. Capacitance
1.0
TJ = 25°C
0.8
V, VOLTAGE (VOLTS)
VBE(sat) @ IC/IB = 10
0.6
VBE(on) @ VCE = 1.0 V
0.4
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
1.0
TJ = 25°C
0.8
IC = 10 mA
50
mA
100 mA
250 mA
500 mA
0.6
0.4
0.2
VCE(sat) @ IC/IB = 10
0
0.5
1.0
2.0
100
5.0
10
20
50
IC, COLLECTOR CURRENT (mA)
200
500
0.2
0
0.05
0.1
0.2
0.5
5.0
10
1.0 2.0
IC, COLLECTOR CURRENT (mA)
20
50
Figure 4. “On” Voltages
Figure 5. Collector Saturation Region
Motorola Small–Signal Transistors, FETs and Diodes Device Data
3
BCP56T1 SERIES
INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
0.15
3.8
0.079
2.0
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.091
2.3
0.079
2.0
0.059
1.5
0.059
1.5
0.091
2.3
0.248
6.3
0.059
1.5
inches
mm
SOT-223
SOT-223 POWER DISSIPATION
The power dissipation of the SOT-223 is a function of the
collector pad size. This can vary from the minimum pad size
for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction tempera-
ture of the die, R
θJA
, the thermal resistance from the device
junction to ambient, and the operating temperature, TA.
Using the values provided on the data sheet for the SOT-223
package, PD can be calculated as follows:
PD =
TJ(max) – TA
R
θJA
power dissipation can be increased. Although the power
dissipation can almost be doubled with this method, area is
taken up on the printed circuit board which can defeat the
purpose of using surface mount technology. A graph of R
θJA
versus collector pad area is shown in Figure 6.
160
R JA , Thermal Resistance, Junction
to Ambient ( C/W)
Board Material = 0.0625″
G-10/FR-4, 2 oz Copper
0.8 Watts
TA = 25°C
140
°
120
1.25 Watts*
1.5 Watts
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 1.5 watts.
PD = 150°C – 25°C = 1.5 watts
83.3°C/W
The 83.3°C/W for the SOT-223 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.5 watts. There are
other alternatives to achieving higher power dissipation from
the SOT-223 package. One is to increase the area of the
collector pad. By increasing the area of the collector pad, the
100
*Mounted on the DPAK footprint
0.2
0.4
0.6
A, Area (square inches)
0.8
1.0
4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
θ
80
0.0
Figure 6. Thermal Resistance versus Collector
Pad Area for the SOT-223 Package (Typical)
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad™. Using a
board material such as Thermal Clad, an aluminum core board,
the power dissipation can be doubled using the same footprint.
BCP56T1 SERIES
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass
or stainless steel with a typical thickness of 0.008 inches.
The stencil opening size for the SOT-223 package should be
the same as the pad size on the printed circuit board, i.e., a
1:1 registration.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•
Always preheat the device.
•
The delta temperature between the preheat and
soldering should be 100°C or less.*
•
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference should be a maximum of 10°C.
•
The soldering temperature and time should not exceed
260°C for more than 10 seconds.
•
When shifting from preheating to soldering, the
maximum temperature gradient should be 5°C or less.
•
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•
Mechanical stress or shock should not be applied during
cooling
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a
figure for belt speed. Taken together, these control settings
make up a heating “profile” for that particular circuit board.
On machines controlled by a computer, the computer
remembers these profiles from one operating session to the
next. Figure 7 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems but it is a good
starting point. Factors that can affect the profile include the
type of soldering system in use, density and types of
components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
150°C
150°C
100°C
100°C
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
50°C
140°C
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 177 –189°C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
STEP 5
STEP 6 STEP 7
STEP 4
HEATING
VENT COOLING
HEATING
ZONES 4 & 7
ZONES 3 & 6
205° TO
“SPIKE”
“SOAK”
219°C
170°C
PEAK AT
SOLDER
160°C
JOINT
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 7. Typical Solder Heating Profile
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
