74F524 8-Bit Registered Comparator
April 1988
Revised August 1999
74F524
8-Bit Registered Comparator
General Description
The 74F524 is an 8-bit bidirectional register with parallel
input and output plus serial input and output progressing
from LSB to MSB. All data inputs, serial and parallel, are
loaded by the rising edge of the input clock. The device
functions are controlled by two control lines (S
0
, S
1
) to exe-
cute shift, load, hold and read out.
An 8-bit comparator examines the data stored in the regis-
ters and on the data bus. Three true-HIGH, open-collector
outputs representing “register equal to bus”, “register
greater than bus” and “register less than bus” are provided.
These outputs can be disabled to the OFF state by the use
of Status Enable (SE). A mode control has also been pro-
vided to allow twos complement as well as magnitude com-
pare. Linking inputs are provided for expansion to longer
words.
Features
s
8-Bit bidirectional register with bus-oriented input-output
s
Independent serial input-output to register
s
Register bus comparator with “equal to”, “greater than”
and “less than” outputs
s
Cascadable in groups of eight bits
s
Open-collector
expansion
comparator
outputs
for
AND-wired
s
Twos complement or magnitude compare
Ordering Code:
Order Number
74F524SC
74F524PC
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009546
www.fairchildsemi.com
74F524
Unit Loading/Fan Out
U.L.
Pin Names
S
0
, S
1
C/SI
CP
SE
M
I/O
0
–I/O
7
Description
HIGH/LOW
Mode Select Inputs
Status Priority or Serial Data Input
Clock Pulse Input (Active Rising Edge)
Status Enable Input (Active LOW)
Compare Mode Select Input
Parallel Data Inputs or
3-STATE Parallel Data Outputs
C/SO
LT
EQ
GT
Note 1:
OC
=
Open Collector
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
70
µA/−0.65
mA
−3
mA/24 mA (20 mA)
−1
mA/20 mA
(Note 1) /20 mA
(Note 1) /20 mA
(Note 1) /20 mA
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
3.5/1.083
150/40 (33.3)
50/33.3
OC (Note 1) /33.3
OC(Note 1) /33.3
OC(Note 1) /33.3
Status Priority or Serial Data Output
Register Less Than Bus Output
Register Equal Bus Output
Register Greater Than Bus Output
Number Representation Select Table
M
L
H
Magnitude Compare
Twos Complement Compare
Operation
Select Truth Table
S
0
L
L
S
1
L
H
Operation
Hold—Retains Data in Shift Register
Read—Read Contents in Register onto Data Bus,
Data Remains in Register Unaffected by Clock
H
H
L
H
Shift—Allows Serial Shifting on Next Rising Clock Edge
Load—Load Data on Bus into Register
Status Truth Table
(Hold Mode)
Inputs
SE
H
L
X
H
H
H
L
C/SI
H
L
L
L
H
H
H
Data Comparison
X
O
A
–O
H
>
I/O
0
–I/O
7
O
A
–O
H
=
I/O
0
–I/O
7
O
A
–O
H
<
I/O
0
–I/O
7
O
A
–O
H
>
I/O
0
–I/O
7
O
A
–O
H
=
I/O
0
–I/O
7
O
A
–O
H
<
I/O
0
–I/O
7
EQ
H
L
H
L
L
H
L
Outputs
GT
H
H
H
H
H
L
L
LT
H
H
H
H
L
L
H
C/SO
1
L
L
L
L
H
L
1
=
HIGH if data are equal, otherwise LOW
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
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2
74F524
Functional Description
The 74F524 contains eight D-type flip-flops connected as a
shift register with provision for either parallel or serial load-
ing. Parallel data may be read from or loaded into the regis-
ters via the data bus I/O
0
–I/O
7
. Serial data is entered from
the C/SI input and may be shifted into the register and out
through the C/SO output. Both parallel and serial data entry
occur on the rising edge of the input clock (CP). The opera-
tion of the shift register is controlled by two signals S
0
and
S
1
according to the Select Truth Table. The 3-STATE paral-
lel output buffers are enabled only in the Read mode.
One port of an 8-bit comparator is attached to the data bus
while the other port is tied to the outputs of the internal reg-
ister. Three active-OFF, open-collector outputs indicate
whether the contents held in the shift register are “greater
than”, (GT), “less than” (LT), or “equal to” (EQ) the data on
the input bus. A HIGH signal on the Status Enable (SE)
input disables these outputs to the OFF state. A mode con-
trol input (M) allows selection between a straightforward
magnitude compare or a comparison between twos com-
plement numbers.
For “greater than” or “less than” detection, the C/SI input
must be held HIGH, as indicated in the Status Truth Table.
The internal logic is arranged such that a LOW signal on
the C/SI input disables the “greater than” and “less than”
outputs. The C/SO output will be forced HIGH if the “equal
to” status condition exists, otherwise C/SO will be held
LOW. These facilities enable the 74F524 to be cascaded
for word length greater than eight bits.
Word length expansion (in groups of eight bits) can be
achieved by connecting the C/SO output of the more signif-
icant byte to the C/SI input of the next less significant byte
and also to its own SE input (see Figure 1). The C/SI input
of the most significant device is held HIGH while the SE
input of the least significant device is held LOW. The corre-
sponding status outputs are AND-wired together. In the
case of twos complement number compare, only the Mode
input to the most significant device should be HIGH. The
Mode inputs to all other cascaded devices are held LOW.
Suppose that an inequality condition is detected in the
most significant device. Assuming that the byte stored in
the register is greater than the byte on the data bus, the EQ
and LT outputs will be pulled LOW and the GT output will
float HIGH. Also the C/SO output of the most significant
device will be forced LOW, disabling the subsequent
devices but enabling its own status outputs. The correct
status condition is thus indicated. The same applies if the
registered byte is less than the data byte, only in this case
the EQ and GT outputs go LOW and LT output floats HIGH.
If an equality condition is detected in the most significant
device, its C/SO output is forced HIGH. This enables the
next less significant device and also disables its own status
outputs. In this way, the status output priority is handed
down to the next less significant device which now effec-
tively becomes the most significant byte. The worst case
propagation delay for a compare operation involving “n”
cascaded 74F524s will be when an equality condition is
detected in all but the least significant byte. In this case, the
status priority has to ripple all the way down the chain
before the correct status output is established. Typically,
this will take 35
+
6(n−2) ns.
Function Diagram
FIGURE 1. Cascading 74F524s for Comparing Longer Words
3
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74F524
Absolute Maximum Ratings
(Note 2)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 3)
Input Current (Note 3)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 2:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
I
OHC
I
CCH
I
CCL
I
CCZ
Output LOW
Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Open Collector, Output
OFF Leakage Test
Power Supply Current
Power Supply Current
Power Supply Current
128
128
128
−60
4.75
3.75
−0.6
70
−650
−150
250
180
180
180
10% V
CC
10% V
CC
2.5
2.4
2.7
2.7
0.5
0.5
5.0
7.0
50
V
µA
µA
µA
V
µA
mA
µA
µA
mA
µA
mA
mA
mA
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
Min
Max
Max
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OL
=
20 mA (I/O
n
)
I
OL
=
24 mA (LT, GT, EQ, C/SO)
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
(I/O
n
, C/SO)
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
I/O
=
2.7V
V
I/O
=
0.5V
V
OUT
=
0V
V
OUT
=
V
CC
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH Z
5
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