INTEGRATED CIRCUITS
74F3893
Quad futurebus backplane transceiver
Product specification
IC15 Data Handbook
1991 Jan 18
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad Futurebus backplane transceiver
74F3893
FEATURES
•
Quad backplane transceiver
•
Drives heavily loaded backplanes with equivalent load
•
Futurebus drivers sink 100mA
•
Reduced voltage swing (1 volt) produces less noise and
reduces power consumption
•
High speed operation enhances performance of backplane
buses and facilitates incident wave switching
•
Compatible with IEEE 896 and IEEE 1194.1 Futurebus
Standards
•
Built–in precision band–gap (BG) reference provides
accurate receiver thresholds and improved noise immunity
•
Glitch–free power up/power down operation on all outputs
impedances down to 10 ohms
much less for BTL, so is its receiver threshold region,
therefore noise margins are excellent.
BTL offers low power consumption, low ground bounce, EMI
and crosstalk, low capacitive loading, superior noise margin
and low propagation delays. This results in a high
bandwidth, reliable backplane.
outputs (Rn) on the receiver
side with a common receiver enable input (RE). It has four
data inputs (Dn) which are also TTL. These data inputs are
NANDed with the data enable input (DE). The four I/O pins
(bus side) are futurebus compatible, sink a minimum of
100mA, and are designed to drive heavily loaded
backplanes with load impedances as low as 10 ohms. All
outputs are designed to be glitch–free during power up and
down.
TYPE
TYPICAL
PROPAGATION DELAY
3.0ns
TYPICAL SUPPLY
CURRENT( TOTAL)
55mA
T
he 74F3893 has four TTL
•
Pin and function compatible with NSC DS3893
DESCRIPTION
The 74F3893 is a quad backplane transceivers and is
intended to be used in very high speed bus systems.
The 74F3893 interfaces to ‘Backplane Transceiver Logic’
(BTL). BTL features a reduced (1V to 2V) voltage swing for
lower power consumption and a series diode on the drivers
to reduce capacitive loading (< 5pF).
Incident wave switching is employed, therefore BTL
propagation delays are short. Although the voltage swing is
74F3893
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
COMMERCIAL RANGE
V
CC
= 5V
±
10%,
T
amb
= 0
°
C to +70
°
C
N74F3893A
PKG DWG #
20-pin PLCC
SOT380-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
D0 – D3
DE
RE
I/O0 – I/O3
I/O0 – I/O3
Data inputs
Data enable input
Receiver enable input
Bus inputs
Bus outputs
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/0.067
1.0/0.33
1.0/0.067
5.0/0.033
OC/166.7
150/40
LOAD VALUE
HIGH/LOW
20µA/40µA
20µA/200µA
20µA/40µA
100µA/20µA
OC/100mA
3mA/24mA
R0 – R7
Receiver outputs
Notes to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
OC= Open collector.
January 18, 1991
2
853-1397 01496
Philips Semiconductors
Product specification
Quad Futurebus backplane transceiver
74F3893
PIN CONFIGURATION
R0
3
D1
R1
LOGIC GND
D2
R2
4
5
6
7
8
9
D3
10
11
12
13
PLCC
BG BUS
D0 V
CC
GND GND
2
1
20
19
18 I/O0
17 I/O1
16 BUS GND
15 I/O2
14 I/O3
FUNCTION TABLE
INPUTS
DE
H
H
H
L
L
L
SF00573
INPUT/
OUT-
PUT
Dn
L
H
Dn
X
X
X
I/On
H
L
Dn
H
H
L
OUT-
PUT
Rn
L
H
Z
Z
L
H
OPERATING
MODE
Transmit to bus
RE
L
L
H
H
L
L
Receiver 3–state,
transmit to bus
Receive, I/On = inputs
R3 DE
RE BUS
GND
LOGIC SYMBOL
2
4
7
9
Notes to function table
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. Z = High impedance ”off” state
LOGIC DIAGRAM
D0
2
18
I/O0
D0 D1 D2 D3
11
12
DE
RE
D1
I/O0 I/O1 1/O2 I/O3
R0 R1 R2 R3
R1
D2
R0
3
4
5
12
7
15
RE
I/O2
17
I/O1
18
V
CC
= Pin 1,
LOGIC GND = Pin 8
BUS GND = Pin 13, 16, 19
BG GND = Pin 20
17
15
14
3
5
8
10
R2
8
9
10
11
SF00574
D3
V
CC
= Pin 1
LOGIC GND = Pin 6
BUS GND = Pin 13, 16, 19
BG GND = Pin 20
R3
DE
14 I/O3
IEC/IEEE SYMBOL
11
12
EN1
EN2
3
18
5
17
7
15
9
9
14
SF00576
2
1D
2
4
7
SF00575
January 18, 1991
3
Philips Semiconductors
Product specification
Quad Futurebus backplane transceiver
74F3893
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
Storage temperature range
PARAMETER
RATING
–1.5 to +6.5
–1.5 to +6.5
–30 to +5
–0.5 to 5.5
200
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
Ik
V
TH
I
OH
I
OL
T
amb
Supply voltage
High–level input voltage
Low–level input voltage
Input clamp current
Bus input threshold
High–level output current
Low–level output current
Operating free air temperature
range
0
I/On only
Rn only
1.475
1.55
Dn, DE, RE
PARAMETER
MIN
4.5
2.0
0.8
–18
1.625
–3
100
+70
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
mA
°
C
January 18, 1991
4
Philips Semiconductors
Product specification
Quad Futurebus backplane transceiver
74F3893
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
I
OH
V
OH
V
OHB
V
OL
V
OLB
V
OCB
V
IK
I
I
I
IH
I
IHB
I
IL
I
ILB
I
OZH
I
OZL
I
OS
PARAMETER
High–level output current
High-level output voltage
High-level output bus voltage
Low-level output voltage
Low-level output
bus voltage
Driver output positive
clamp voltage
Input clamp voltage
Input current at maximum input voltage
High–level input current
High–level I/O bus current
(power off)
Low–level input current
Low–level I/O bus current
(power on)
Off–state output current,
high–level voltage applied
Off–state output current,
low–level voltage applied
Short circuit output current
3
Rn
’F8
Dn, RE, DE
I/On
Dn, RE
DE
I/On
Rn
I/On
I/On
Rn
I/On
Rn
I/On
TEST
CONDITIONS
1
V
CC
= MAX, V
IL
= MAX, V
IH
= MIN, V
OH
= 1.5V
V
CC
= MAX, V
IL
= 1.3V, RE = 0.8V, I
OH
= MAX
V
CC
= MAX, Dn = DE = 0.8V, V
T
= 2.0V,
R
T
= 10Ω, RE = 2.0V
V
CC
= MIN, V
IN
= 1.8V, RE = 0.8V, I
OL
= 6mA
Dn = DE = V
IH
, I
OL
= 100mA
Dn = DE = V
IH
, I
OL
= 80mA
V
CC
= MAX or 0V,
Dn = DE = 0.8V, RE = 2.0V
V
CC
= MIN, I
I
=I
IK
V
CC
= MAX, V
I
= 7.0V, DE = RE = Dn = V
CC
V
CC
= MAX, DE = RE = Dn =5.5V
V
CC
= 0V, Dn = DE = 0.8V, I/On =1.2V, RE = 0V
V
CC
= MAX, V
I
= 0.5V, DE = 4.5V
V
CC
= MAX, V
I
= 0.5V, Dn = 4.5V
V
CC
= MAX, Dn = DE = 0.8V, I/On =0.75V,
RE = 0V
V
CC
= MAX, V
I
= 2.7V, RE = 2V
V
CC
= MAX, V
I
= 0.5V, RE = 2V
V
CC
= MAX
-60
I/On = 1mA
I/On = 10mA
0.75
0.75
1.9
2.3
–0.73
2.5
2.5
0.35
1.0
1.0
0.5
1.2
1.1
2.9
3.2
-1.2
100
20
100
–40
–200
–20
20
20
–20
-150
MIN
LIMITS
TYP
2
10
MAX
100
µA
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
mA
UNIT
I
CC
Supply current
4
(total)
V
CC
= MAX, (RE = V
IH
or V
IL
)
55
80
mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
January 18, 1991
5
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