74F382 4-Bit Arithmetic Logic Unit
May 1988
Revised August 1999
74F382
4-Bit Arithmetic Logic Unit
General Description
The 74F382 performs three arithmetic and three logic oper-
ations on two 4-bit words, A and B. Two additional Select
input codes force the Function outputs LOW or HIGH. An
Overflow output is provided for convenience in twos com-
plement arithmetic. A Carry output is provided for ripple
expansion. For high-speed expansion using a Carry Looka-
head Generator, refer to the 74F381 data sheet.
Features
s
Performs six arithmetic and logic functions
s
Selectable LOW (clear) and HIGH (preset) functions
s
LOW input loading minimizes drive requirements
s
Carry output for ripple expansion
s
Overflow output for twos complement arithmetic
Ordering Code:
Order Number
74F382SC
74F382SJ
74F382PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009529
www.fairchildsemi.com
74F382
Unit Loading/Fan Out
Pin Names
A
0
–A
3
B
0
–B
3
S
0
–S
2
C
n
C
n
+
4
OVR
F
0
–F
3
Description
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
Carry Output
Overflow Output
Function Outputs
U.L.
HIGH/LOW
1.0/4.0
1.0/4.0
1.0/1.0
1.0/5.0
50/33.3
50/33.3
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−2.4
mA
20
µA/−2.4
mA
20
µA/−0.6
mA
20
µA/−3.0
mA
−1
mA/20 mA
−1
mA/20 mA
−1
mA/20 mA
Functional Description
Signals applied to the Select inputs S
0
–S
2
determine the
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW oper-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the C
n
input of the least significant package.
Ripple expansion is illustrated in Figure 2. The overflow
output OVR is the Exclusive-OR of C
n
+
3
and C
n
+
4
; a
HIGH signal on OVR indicates overflow in twos comple-
ment operation. Typical delays for Figure 2 are given in
Figure 1.
Function Select Table
Select
S
0
L
H
L
H
L
H
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
S
1
L
L
H
H
L
L
H
H
S
2
L
L
L
L
H
H
H
H
Operation
Clear
B Minus A
A Minus B
A Plus B
A
⊕
B
A
+
B
AB
Preset
Path Segment
A
1
or B
1
to C
n
+
4
C
n
to C
n
+
4
C
n
to C
n
+
4
C
n
to F
C
n
to C
n
+
4
, OVR
Total Delay
Toward
F
6.5 ns
6.3 ns
6.3 ns
8.1 ns
—
27.2 ns
Output
C
n
+
4
, OVR
6.5 ns
6.3 ns
6.3 ns
—
8.0 ns
27.1 ns
FIGURE 1. 16-Bit Delay Tabulation
FIGURE 2. 16-Bit Ripply Carry ALU Expansion
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2
74F382
Truth Table
Inputs
Function
CLEAR
B MINUS A
S
0
L
H
S
1
L
L
S
2
L
L
C
n
L
H
L
L
L
L
H
H
H
H
A MINUS B
L
H
L
L
L
L
L
H
H
H
H
A PLUS B
H
H
L
L
L
L
L
H
H
H
H
A
⊕
B
L
L
H
X
X
L
X
H
A
+
B
H
L
H
X
X
X
L
H
AB
L
H
H
X
X
X
L
H
PRESET
H
H
H
X
X
X
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Outputs
A
n
X
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
B
n
X
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
H
H
L
H
L
H
H
L
H
L
H
H
F
0
L
L
H
L
L
H
L
H
H
L
H
L
L
H
L
H
H
L
L
H
H
L
H
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
F
1
L
L
H
H
L
H
L
H
L
L
H
L
H
H
L
L
H
L
L
H
H
H
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
F
2
L
L
H
H
L
H
L
H
L
L
H
L
H
H
L
L
H
L
L
H
H
H
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
F
3
L
L
H
H
L
H
L
H
L
L
H
L
H
H
L
L
H
L
L
H
H
H
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
OVR
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
C
n
+
4
H
H
L
H
L
L
H
H
L
H
L
L
H
L
H
L
H
H
L
L
L
H
L
H
H
H
L
L
L
H
H
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
X
=
Immaterial
3
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74F382
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74F382
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
over Operating Temperature Range unless otherwise specified
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
4.75
3.75
−0.6
−2.4
−3.0
I
OS
I
CC
Output Short-Circuit Current
Power Supply Current
−60
54
−150
81
mA
mA
Max
Max
mA
Max
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
Min
Min
Min
Max
Max
Max
0.0
0.0
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (S
0
– S
2
)
V
IN
=
0.5V (A
0
– A
3
, B
0
– B
3
)
V
IN
=
0.5V (C
n
)
V
OUT
=
0V
5
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