74F323 Octal Universal Shift/Storage Register
April 1988
Revised August 1999
74F323
Octal Universal Shift/Storage Register
with Synchronous Reset and Common I/O Pins
General Description
The 74F323 is an 8-bit universal shift/storage register with
3-STATE outputs. Its function is similar to the 74F299 with
the exception of Synchronous Reset. Parallel load inputs
and flip-flop outputs are multiplexed to minimize pin count.
Separate serial inputs and outputs are provided for Q
0
and
Q
7
to allow easy cascading. Four operation modes are
possible: hold (store), shift left, shift right and parallel load.
Features
s
Common parallel I/O for reduced pin count
s
Additional serial inputs and outputs for expansion
s
Four operating modes: shift left, shift right, load and
store
s
3-STATE outputs for bus-oriented applications
Ordering Code:
Order Number
74F323SC
74F323PC
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009517
www.fairchildsemi.com
74F323
Unit Loading/Fan Out
Pin Names
CP
DS
0
DS
7
S
0,
S
1
SR
OE
1,
OE
2
I/O
0
–I/O
7
Q
0,
Q
7
Description
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Reset Input (Active LOW)
3-STATE Output Enable Inputs (Active LOW)
Multiplexed Parallel Data Inputs
3-STATE Parallel Data Outputs
Serial Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
3.5/1.083
150/40 (33.3)
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−1.2
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
70
µA/−0.65
mA
−3
mA/24 mA (20 mA)
−1
mA/20 mA
Functional Description
The 74F323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0
and S
1
as shown
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Logic Diagram
Mode Select Table
Inputs
SR S
1
L
H
H
H
H
X
H
L
H
L
S
0
CP
X
H
H
L
L
Response
X
Synchronous Reset; Q
0
–Q
7
=
LOW
Parallel Load; I/O
n
→
Q
n
Shift Right; DS
0
→
Q
0,
Q
0
→
Q
1,
etc.
Shift Left; DS
7
→
Q
7,
Q
7
→
Q
6,
etc.
Hold
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH transition
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
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2
74F323
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
Output LOW
Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
68
68
68
−60
4.75
3.75
−0.6
−1.2
−150
500
95
95
95
10% V
CC
10% V
CC
2.5
2.4
2.7
2.7
0.5
0.5
5.0
7.0
0.5
50
V
µA
µA
mA
µA
V
µA
mA
mA
mA
µA
mA
mA
mA
Min
Max
Max
Max
Max
0.0
0.0
Max
Max
Max
0.0V
Max
Max
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA (Q
0
, Q
7
)
I
OH
= −3
mA (I/O
n
)
I
OH
= −1
mA (Q
0
, Q
7
)
I
OH
= −3
mA (I/O
n
)
I
OL
=
20 mA (Q
0
, Q
7
)
I
OL
=
24 mA (I/O
n
)
V
IN
=
2.7V
V
IN
=
7.0V (Non I/O Inputs)
V
IN
=
5.5V (I/O Inputs)
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
IN
=
0.5V
V
OUT
=
0V
V
OUT
=
5.25V
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH Z
(CP, DS
0
, DS
7
, SR, OE
1
, OE
2
)
(S
0
, S
1
)
3
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74F323
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Enable Time
S
n
to I/O
n
Output Disable Time
S
n
to I/O
n
Output Disable Time
Maximum Input Frequency
Propagation Delay
CP to Q
0
or Q
7
Propagation Delay
CP to I/O
n
Output Enable Time
70
4.0
4.5
3.5
4.0
3.5
4.0
2.0
1.0
3.5
4.0
2.5
1.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
100
7.0
6.5
7.0
8.5
6.0
7.0
4.5
4.0
8.0
8.0
9.0
9.0
8.0
10.0
6.0
5.5
9.0
10.0
6.0
5.5
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
70
4.0
4.5
3.5
4.0
3.5
4.0
2.0
1.0
3.5
4.0
2.5
1.5
8.5
8.5
10.0
10.0
9.0
11.0
7.0
6.5
10.0
11.0
7.0
6.5
ns
ns
ns
ns
Max
MHz
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
Setup Time, HIGH or LOW
S
0
or S
1
to CP
Hold Time, HIGH or LOW
S
0
or S
1
to CP
Setup Time, HIGH or LOW
I/O
n
, DS
0
, DS
7
to CP
Hold Time, HIGH or LOW
I/O
n
, DS
0
, DS
7
to CP
Setup Time, HIGH or LOW
SR to CP
Hold Time, HIGH or LOW
SR to CP
CP Pulse Width
HIGH or LOW
8.5
8.5
0
0
5.0
5.0
2.0
2.0
10.0
10.0
0
0
5.0
5.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
8.5
8.5
0
0
5.0
5.0
2.0
2.0
10.0
10.0
0
0
5.0
5.0
ns
ns
ns
ns
Max
Units
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4
74F323
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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