74F299 Octal Universal Shift/Storage Register
April 1988
Revised August 1999
74F299
Octal Universal Shift/Storage Register
with Common Parallel I/O Pins
General Description
The 74F299 is an 8-bit universal shift/storage register with
3-STATE outputs. Four modes of operation are possible:
hold (store), shift left, shift right and load data. The parallel
load inputs and flip-flop outputs are multiplexed to reduce
the total number of package pins. Additional outputs, Q
0
–
Q
7
, are provided to allow easy serial cascading. A separate
active LOW Master Reset is used to reset the register.
Features
s
Common parallel I/O for reduced pin count
s
Additional serial inputs and outputs for expansion
s
Four operating modes: shift left, shift right, load and
store
s
3-STATE outputs for bus-oriented applications
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number
74F299SC
74F299SJ
74F299PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009515
www.fairchildsemi.com
74F299
Unit Loading/Fan Out
Pin Names
CP
DS
0
DS
7
S
0
, S
1
MR
OE
1
, OE
2
I/O
0
–I/O
7
Q
0
, Q
7
Description
Clock Pulse Input (Active Rising Edge)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset Input (Active LOW)
3-STATE Output Enable Inputs (Active LOW)
Parallel Data Inputs or
3-STATE Parallel Outputs
Serial Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
3.5/1.083
150/40(33.3)
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−1.2
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
70
µA/−0.65
mA
−3
mA/24 mA (20 mA)
−1
mA/20 mA
Functional Description
The 74F299 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
shift left, shift right, parallel load and hold operations. The
type of operation is determined by S
0
and S
1
, as shown in
the Mode Select Table. All flip-flop outputs are brought out
through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE outputs are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Logic Diagram
Mode Select Table
Inputs
MR S
1
S
0
CP
L
H
H
H
H
X
H
L
H
L
X
H
H
L
L
Response
X Asynchronous Reset; Q
0
–Q
7
=
LOW
Parallel Load; I/O
n
→
Q
n
Shift Right; DS
0
→
Q
0
, Q
0
→
Q
1
, etc.
Shift Left; DS
7
→
Q
7
, Q
7
→
Q
6
, etc.
X Hold
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
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2
74F299
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
ESD Last Passing Voltage (Min)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
−0.5V
to
+5.5V
twice the rated I
OL
(mA)
−0.5V
to V
CC
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
BVIT
I
CEX
V
ID
I
OD
I
IL
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
4.75
3.75
−0.6
−1.2
Output Leakage
Current
Output Leakage
Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
68
68
68
−60
70
−650
−150
500
95
95
95
µA
µA
mA
µA
mA
mA
mA
Max
Max
Max
0.0V
Max
Max
Max
10% V
CC
10% V
CC
2.5
2.4
2.7
2.7
0.5
0.5
5.0
µA
µA
mA
µA
V
µA
mA
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
Min
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA (Q
0
, Q
7
, I/O
n
)
I
OH
= −3
mA (I/O
n
)
I
OH
= −1
mA (Q
0
, Q
7
, I/O
n
)
I
OH
= −3
mA (I/O
n
)
I
OL
=
20 mA (Q
0
, Q
7
)
I
OL
=
24 mA (I/O
n
)
V
IN
=
2.7V (CP, DS
0
, DS
7
, S
0
, S
1
,
MR, OE
1
, OE
2
)
V
IN
=
7.0V (CP, DS
0
, DS
7
, S
0
, S
1
,
MR, OE
1
, OE
2
)
V
IN
=
5.5V (I/O
n
)
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (CP, DS
0
, DS
7
, MR, OE
1
, OE
2
)
V
IN
=
0.5V (S
0
, S
1
)
V
I/O
=
2.7V (I/O
n
)
V
I/O
=
0.5V (I/O
n
)
V
OUT
=
0V
V
OUT
=
5.25V
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH Z
7.0
0.5
50
Max
Max
Max
0.0
0.0
Max
3
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74F299
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Input Frequency
Propagation Delay
CP to Q
0
or Q
7
Propagation Delay
CP to I/O
n
Propagation Delay
MR to Q
0
or Q
7
Propagation Delay
MR to I/O
n
Output Enable Time
OE to I/O
n
Output Disable Time
OE to I/O
n
Output Enable Time
S
n
to I/O
n
Output Disable Time
S
n
to I/O
n
70
4.0
4.5
3.5
4.0
5.5
V
CC
=
5.0V
C
L
=
50 pF
Typ
100
7.0
6.5
7.0
8.5
7.5
8.0
8.0
9.0
9.0
9.5
Max
T
A
= −55°C
to
+125°C
V
CC
=
5.0V
C
L
=
50 pF
Min
85
4.0
4.5
3.5
4.0
5.5
9.0
9.5
10.0
11.0
12.5
Max
T
A
=
0 to
+70°C
V
CC
=
5.0V
C
L
=
50 pF
Min
70
4.0
4.5
3.5
4.0
5.5
8.5
8.5
10.0
10.0
10.5
ns
5.5
3.5
4.0
2.0
1.0
3.5
4.0
2.5
1.5
11.0
6.0
7.0
4.5
4.0
10.0
8.0
10.0
6.0
5.5
9.0
10.0
6.0
5.5
5.5
3.0
4.0
1.5
1.0
3.0
4.0
1.5
1.0
12.0
9.5
13.0
7.0
6.5
10.5
13.0
7.0
6.5
5.5
3.5
4.0
2.0
1.0
3.5
4.0
2.5
1.5
10.5
9.0
11.0
7.0
6.5
10.0
11.0
7.0
6.5
ns
ns
ns
ns
Max
MHz
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
=
5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
S
0
or S
1
to CP
Hold Time, HIGH or LOW
S
0
or S
1
to CP
Setup Time, HIGH or LOW
I/O
n
, DS
0
or DS
7
to CP
Hold Time, HIGH or LOW
I/O
n
, DS
0
or DS
7
to CP
CP Pulse Width
HIGH or LOW
MR Pulse Width, LOW
Recovery Time, MR to CP
8.5
8.5
0
0
5.0
5.0
2.0
2.0
5.0
5.0
5.0
7.0
Max
T
A
= −55°C
to
+125°C
V
CC
=
5.0V
Min
10.0
7.5
0
0
5.0
5.0
2.0
2.0
5.0
5.0
6.0
12.0
Max
T
A
=
0 to
+70°C
V
CC
=
5.0V
Min
8.5
8.5
0
0
5.0
5.0
2.0
2.0
5.0
5.0
5.0
7.0
ns
ns
ns
ns
ns
Max
Units
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4
74F299
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number MD20D
5
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