INTEGRATED CIRCUITS
74F2244
Octal buffer with 30Ω equivalent output
termination (3-State)
Product specification
IC15 Data Handbook
1994 Dec 5
Philips Semiconductors
Philips Semiconductors
Product specification
Octal buffer with 30Ω equivalent output termination
(3-State)
74F2244
FEATURES
•
Octal bus interface
•
30Ω output termination ideal for driving DRAM
•
15mA source current
•
SSOP Type II Package
DESCRIPTION
The 74F2244 is an octal buffer that is ideal for driving dynamic
DRAM with matching impedance. The outputs are all capable of
sinking 5mA and sourcing up to 15mA. The device features two
output enables, OEa and OEb, each controlling four of the 3–state
outputs.
TYPICAL
PROPAGATION
DELAY
4.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
30mA
TYPE
74F2244
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
20-pin plastic DIP
20-pin plastic SOL
20-pin plastic SSOP Type II
COMMERCIAL RANGE
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
N74F2244N
N74F2244D
N74F2244DB
DRAWING NUMBER
SOT146-1
SOT163-1
SOT339-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
Ian, Ibn
OEa, OEb
Data inputs
Output enable inputs (active low)
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/0.33
1.0/0.33
LOAD VALUE
HIGH/LOW
20µA/0.2mA
20µA/0.2mA
15mA/5mA
Yan, Ybn
Data outputs
750/8.33
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
OEa 1
Ia0 2
Yb0 3
Ia1 4
Yb1 5
Ia2 6
Yb2 7
Ia3 8
Yb3 9
GND 10
20 V
CC
19 OEb
18 Ya0
17 Ib0
16 Ya1
15 Ib1
14 Ya2
13 Ib2
12 Ya3
11 Ib3
LOGIC SYMBOL
2
4
6
8
17
15
13
11
Ia0
1
19
OEa
OEb
Ia1
Ia2
Ia3 Ib0
Ib1
Ib2
Ib3
Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3
18
V
CC
= Pin 20
GND = Pin 10
16
14
12
3
5
7
9
SF00227
SF00228
1994 Dec 05
2
853-1525 14380
Philips Semiconductors
Product specification
Octal buffer with 30Ω equivalent output termination
(3-State)
74F2244
IEC/IEEE SYMBOL
1
19
EN1
EN2
LOGIC DIAGRAM
Ia0
2
18
Ya0
Ib0
17
2
Yb0
2
4
6
8
17
15
13
11
2D
1
18
16
14
12
Ia1
4
16
Ya1
Ib1
15
5
Yb1
Ia2
6
14
Ya2
Ib2
13
7
Yb2
2
3
5
7
9
Ia3
8
12
Ya3
Ib3
11
9
Yb3
OEa
1
OEb
10
V
CC
= Pin 20
GND = Pin 10
SF00229
SF00236
FUNCTION TABLE
INPUTS
OEa
L
L
H
Ia
L
H
X
OEb
L
L
H
Ib
L
H
X
OUTPUTS
Ya
L
H
Z
Yb
L
H
Z
Notes to function table
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance ”off” state
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in high output state
Current applied to output in low output state
Operating free air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
10
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
1994 Dec 05
Supply voltage
High–level input voltage
Low–level input voltage
Input clamp current
High–level output current
Low–level output current
Operating free air temperature range
0
PARAMETER
PARAMETER
MIN
4.5
2.0
0.8
–18
–15
5
+70
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
UNIT
°
C
3
Philips Semiconductors
Product specification
Octal buffer with 30Ω equivalent output termination
(3-State)
74F2244
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
V
CC
= MIN,
V
OH
High-level output voltage
V
IL
= MAX,
V
IH
= MIN
I
OH
=
–15mA
TEST
CONDITIONS
1
I
OH
= –3mA
±10%V
C
±5%V
CC
±10%V
C
±5%V
CC
±10%V
C
C
C
C
LIMITS
MIN
2.5
2.7
2.0
2.0
0.50
0.42
–0.73
0.50
-1.2
100
20
–0.2
50
–50
-60
20
-150
30
65
40
3.4
TYP
2
MAX
UNIT
V
V
V
V
V
V
V
µA
µA
mA
µA
µA
mA
mA
mA
mA
V
OL
Low-level output voltage
V
CC
= MIN,
V
IL
= MAX,
V
IH
= MIN,
V
CC
= MIN, I
I
= I
IK
I
OL
= MAX
±5%V
CC
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Input clamp voltage
Input current at maximum input voltage
High–level input current
Low–level input current
Off–state output current,
high–level voltage applied
Off–state output current,
low–level voltage applied
Short–circuit output current
3
I
CCH
Supply current (total)
I
CCL
I
CCZ
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
O
= 2.7V
V
CC
= MAX, V
O
= 0.5V
V
CC
= MAX
V
CC
= MAX
45
26
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25
°
C
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500Ω
MIN
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Ian, Ibn to Yn
Output enable time
to high or low level
Output disable time
from high or low level
Waveform 1
Waveform 2
Waveform 3
Waveform 2
Waveform 3
3.0
2.5
2.5
3.0
1.5
1.5
TYP
4.5
4.5
4.5
5.0
3.5
2.5
MAX
7.0
7.0
7.5
8.0
6.0
5.5
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
2.5
2.5
2.0
3.0
1.0
1.0
MAX
8.0
7.5
8.0
8.5
6.0
5.5
ns
ns
ns
T
amb
= 0
°
C to +70
°
C
UNIT
1994 Dec 05
4
Philips Semiconductors
Product specification
Octal buffer with 30Ω equivalent output termination
(3-State)
74F2244
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
Ian, Ibn
V
M
V
M
t
PHL
OEn
V
M
t
PZL
V
M
t
PLZ
3.5V
t
PLH
Yn
V
M
V
M
Yn
V
M
V
OL
+0.3V
SF00234
SF00231
Waveform 1. Propagation delay for data to outputs
Waveform 3. 3-State output enable time to low level
and output disable time from low level
OEn
V
M
V
M
t
PZH
t
PHZ
V
OH
–0.3V
0V
Yn
V
M
SF00233
Waveform 2. 3-State output enable time to high level
and output disable time from high level
TEST CIRCUIT AND WAVEFORMS
SWITCH POSITION
TEST
SWITCH
t
PLZ
, t
PZL
closed
All other
open
V
IN
PULSE
GENERATOR
R
T
D.U.T.
t
TLH (
t
r
)
C
L
R
L
POSITIVE
PULSE
10%
90%
V
M
t
w
t
THL (
t
f
)
AMP (V)
90%
V
M
10%
0V
V
CC
7.0V
90%
NEGATIVE
PULSE
V
M
10%
V
OUT
R
L
t
THL (
t
f
)
t
w
V
M
10%
t
TLH (
t
r
)
0V
90%
AMP (V)
Test circuit for 3-State outputs
DEFINITIONS:
R
L
= Load resistor; see AC electrical characteristics for
value.
C
L
= Load capacitance includes jig and probe
capacitance; see AC electrical characteristics for
value
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
Input pulse definition
INPUT PULSE REQUIREMENTS
family
amplitude
74F
3.0V
V
M
1.5V
rep. rate
1MHz
t
w
t
TLH
t
THL
2.5ns
SF000235
500ns 2.5ns
1994 Dec 05
5
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