Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
FEATURES
•
Provides 16 arithmetic operation: add, subtract, compare, and
double; plus 12 other arithmetic operations
PIN CONFIGURATION
B0 1
A0
S3
S2
S1
S0
Cn
M
2
3
4
5
6
7
8
9
24 V
CC
23 A1
22 B1
21 A2
20 B2
19 A3
18 B3
17 G
16 C
n+4
15 P
14 A=B
13 F3
•
Provides all 16 logic operations of two variables: Exclusive-OR,
Compare, AND, NAND, NOR, OR, plus 10 other logic operations
•
Full look-ahead carry for high speed arithmetic operation on long
words
•
40% faster than ’S181 with only 30% ’S181 power consumption
•
Available in 300mil-wide Slim 24-pin Dual In-Line package
DESCRIPTION
The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit
(ALU). Controlled by the four Function Select inputs (S0–S3) and
the Mode Control input (M), it can perform all the 16 possible logic
operations or 16 different arithmetic operations on active-High or
active-Low operands. The Function Table lists these operations.
F0
F1 10
F2 11
GND 12
SF00193
TYPE
74F181
TYPICAL PROPAGATION DELAY
7.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
43mA
ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic Slim DIP (300 mil)
24-Pin Plastic SOL
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F181N
N74F181D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
A0–A3
B0–B3
M
S0–S3
Cn
C
n+4
P
G
A=B
F0–F3
NOTE:
DESCRIPTION
A operand inputs
B operand inputs
Mode control input
Function select input
Carry input
Carry output
Carry Propagate output
Carry Generate output
Compare output
Outputs
74F (U.L.) HIGH/LOW
1.0/3.0
1.0/3.0
1.0/1.0
1.0/4.0
1.0/5.0
50/33
50/33
50/33
OC/33
50/33
LOAD VALUE HIGH/LOW
20µA/1.8mA
20µA/1.8mA
20µA/0.6mA
20µA/2.4mA
20µA/3.0mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
OC/20mA
1.0mA/20mA
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
OC = Open Collector
March 3, 1989
1
853–0351 95947
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
When the Mode Control input (M) is High, all internal carries are
inhibited and the device performs logic operations on the individual
bits as listed. When the Mode control input is Low, the carries are
enabled and the device performs arithmetic operations on the two
4-bit words. The device incorporates full internal carry look-ahead
and provides for either ripple carry between device using the C
n+4
output, or for carry look-ahead between packages using the signals
P (Carry Propagate) and G (Carry Generate). P and G are not
affected by carry in. When speed requirements are not stringent, it
can be used in a simple ripple carry mode by connecting the Carry
output (C
n+4
) signal to the Carry input (Cn) of the next unit. For
high-speed operation, the device is used in conjunction with the
74F182 carry look-ahead circuit. One carry look-ahead package is
required for each group of four 74F181 devices. Carry look-ahead
can be provided at various levels and offers high speed capability
over extremely long word lengths.
The A=B output from the device goes High when all four F outputs
are High and can be used to indicate logic equivalence over 4-bits
when the unit is in the subtract mode. The A=B output is
open-collector and can be wired-AND with other A=B outputs to give
a comparison for more than 4 bits. The A=B signal can also be used
with the C
n+4
signal to indicate A>B and A<B. The Function Table
lists the arithmetic operations that are performed without a carry in.
An incoming carry adds a one to each operation. Thus select code
LHHL generates A minus B minus 1 (two’s complement notation)
without a carry in and generates A minus B when a carry is applied.
Because subtraction is actually performed by complementary
addition (one’s complement), a carry out means borrow; thus, a
carry is generated when there is no underflow and no carry is
generated when there is underflow. As indicated, this device can be
used with either active-Low inputs producing active-Low outputs or
with active-High inputs producing active-High outputs. For either
case, the table lists the operations that are performed to the
operands labeled inside the logic symbol.
MODE-SELECT FUNCTION TABLE
MODE SELECT INPUTS
S3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
*
**
=
=
=
=
S2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
S1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
S0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
ACTIVE HIGH INPUTS & OUTPUTS
Logic (M=H)
A
A+B
AB
Logical 0
AB
B
A⊕B
AB
A+B
A⊕B
B
AB
Logical 1
A+B
A+B
A
Arithmetic** (M=L) (Cn=H)
A
A+B
A+B
minus 1
A plus AB
(A+B) plus AB
A minus B minus 1
AB minus 1
A plus AB
A plus B
(A+B) plus AB
AB minus 1
A plus A*
(A+B) plus A
(A+B) plus A
A minus 1
ACTIVE LOW INPUTS & OUTPUTS
Logic (M=H)
A
AB
A+B
Logical 1
A+B
B
A⊕B
A+B
AB
A⊕B
B
A+B
Logical 0
AB
AB
A
Arithmetic** (M=L) (Cn=L)
A minus 1
AB minus 1
AB minus 1
minus 1
A plus (A+B)
AB plus (A+B)
A minus B minus 1
A+B
A plus (A+B)
A plus B
AB plus (A+B)
A+B
A plus A*
AB plus A
AB plus A
A
High voltage level
Low voltage level
Each bit is shifted to the next more significant position.
Arithmetic operations expressed in two’s complement notation.
March 3, 1989
4
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
Table 1. Sum Mode Test
Function Inputs: S0 = S3 = 4.5V, S1 = S2 = M = 0V
PARAMETER
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
INPUT
UNDER TEST
A
i
B
i
A
i
B
i
A
i
B
i
A
i
B
i
Cn
OTHER INPUT, SAME BIT
Apply 4.5V
B
i
A
i
B
i
A
i
None
None
None
None
None
Apply GND
None
None
None
None
B
i
A
i
B
i
A
i
None
OTHER DATA INPUTS
Apply 4.5V
Remaining A and B
Remaining A and B
None
None
Remaining B
Remaining B
Remaining B
Remaining B
All A
Apply GND
Cn
Cn
Remaining A, B, Cn
Remaining A, B, Cn
Remaining A, Cn
Remaining A, Cn
Remaining A, Cn
Remaining A, Cn
All B
OUTPUT
UNDER TEST
F
i
F
i
P
P
G
G
C
n+4
C
n+4
Any F or C
n+4
Table 2. Diff Mode Test
Function Inputs: S1 = S2 = 4.5V, S0 = S3 = M = 0V
PARAMETER
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLH
, t
PHL
INPUT
UNDER TEST
A
i
B
i
A
i
B
i
A
i
B
i
A
i
B
i
A
i
B
i
Cn
OTHER INPUT, SAME BIT
Apply 4.5V
None
A
i
None
A
i
B
i
None
None
A
i
B
i
None
None
Apply GND
B
i
None
B
i
None
None
A
i
B
i
None
None
A
i
None
OTHER DATA INPUTS
Apply 4.5V
Remaining A
Remaining A
None
None
None
None
Remaining A
Remaining A
None
None
All A and B
Apply GND
Remaining B, Cn
Remaining B, Cn
Remaining A, B, Cn
Remaining A, B, Cn
Remaining A, B, Cn
Remaining A, B, Cn
Remaining B, Cn
Remaining B, Cn
Remaining A, B, Cn
Remaining A, B, Cn
None
OUTPUT
UNDER TEST
F
i
F
i
P
P
G
G
A=B
A=B
C
n+4
C
n+4
Any F or C
n+4
Table 3. Logic Mode Test
Function Inputs: S1 = S2 = 4.5V, S0 = S3 = 0V
PARAMETER
t
PLH
, t
PHL
t
PLH
, t
PHL
INPUT
UNDER TEST
A
i
B
i
OTHER INPUT, SAME BIT
Apply 4.5V
B
i
A
i
Apply GND
None
None
OTHER DATA INPUTS
Apply 4.5V
None
None
Apply GND
Remaining A, B, Cn
Remaining A, B, Cn
OUTPUT
UNDER TEST
F
i
F
i
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
March 3, 1989
5
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