INTEGRATED CIRCUITS
74F174
Hex D flip-flops
Product specification
IC15 Data Handbook
1988 Oct 07
Philips
Semiconductors
Philips Semiconductors
Product specification
Hex D flip-flop
74F174
FEATURES
•
Six edge-triggered D-type flip-flops
•
Buffered common Clock
•
Buffered, asynchronous Master Reset
DESCRIPTION
The 74F174 has six edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common buffered Clock (CP) and Master
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where true outputs only are required, and the Clock and
Master Reset are common to all storage elements.
TYPICAL
SUPPLY CURRENT
(TOTAL)
35mA
PIN CONFIGURATION
MR
Q0
D0
D1
Q1
D2
Q2
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q5
D5
D4
Q4
D3
Q3
CP
SF00188
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
16-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F174N
N74F174D
PKG DWG #
SOT38-4
SOT109-1
TYPE
74F174
TYPICAL f
MAX
100MHz
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0–D5
CP
MR
Q0–Q5
Data inputs
Clock Pulse input (active rising edge)
Master Reset input (active-Low)
Outputs
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
3
4
6
11
13
14
IEC/IEEE SYMBOL
9
1
C1
R
D0
9
1
CP
MR
D1
D2
D3
D4
D5
3
4
6
1D
2
5
7
10
12
15
Q0
Q1
Q2
Q3
Q4
Q5
11
13
2
V
CC
= Pin 16
GND = Pin 8
5
7
10
12
15
14
SF00189
SF00190
October 7, 1988
2
853–0060 94766
Philips Semiconductors
Product specification
Hex D flip-flop
74F174
LOGIC DIAGRAM
D0
3
D1
4
D2
6
D3
11
D4
13
D5
14
D
CP
R
D
CP
MR
9
1
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
2
V
CC
= Pin 16
GND = Pin 8
Q0
Q1
5
Q2
7
Q3
10
Q4
12
Q5
15
SF00192
FUNCTION TABLE
INPUTS
MR
L
H
H
CP
X
↑
↑
D
X
h
l
OUTPUTS
Qn
L
H
L
OPERATING MODE
Reset (clear)
Load “1”
Load “0”
H = High voltage level
L = Low voltage level
X = Don’t care
↑
= Low-to-High Clock transition
h = High voltage level one set-up time prior to the Low-to-High Clock transition.
l = Low voltage level one set-up time prior to the Low-to-High Clock transition.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
20
+70
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
October 7, 1988
3
Philips Semiconductors
Product specification
Hex D flip-flop
74F174
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OH
= MAX
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
3
Supply current (total)
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX, Dn = MR = 4.5V, CP =
↑
–60
35
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
LIMITS
MIN
2.5
V
2.7
3.4
0.30
0.30
–0.73
0.50
V
0.50
–1.2
100
20
–0.6
–150
45
V
µA
µA
mA
mA
mA
TYP
2
MAX
UNIT
V
O
OH
High-level
High level output voltage
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PHL
Maximum clock frequency
Propagation delay
CP to Qn
Propagation delay MR to Qn
Waveform 1
Waveform 1
Waveform 2
80
3.5
4.5
5.0
TYP
100
5.5
6.0
8.5
8.0
10.0
14.0
MAX
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF, R
L
= 500Ω
MIN
80
3.5
4.5
5.0
9.0
11.0
15.0
MAX
MHz
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF, R
L
= 500Ω
MIN
t
S
(H)
t
S
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
REC
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
CP Pulse width,
High or Low
MR Pulse width, Low
Recovery time, MR to CP
Waveform 3
Waveform 3
Waveform 1
Waveform 2
Waveform 2
4.0
4.0
0.0
0.0
4.0
6.0
5.0
5.0
TYP
MAX
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF, R
L
= 500Ω
MIN
4.0
4.0
0.0
0.0
4.0
6.0
5.0
5.0
MAX
ns
ns
ns
ns
ns
UNIT
October 7, 1988
4
Philips Semiconductors
Product specification
Hex D flip-flop
74F174
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
t
w
(L)
CP
V
M
t
w
(H)
t
PHL
Qn
V
M
t
PLH
CP
V
M
V
M
V
M
V
M
Dn
V
M
t
s
(H)
V
M
t
h
(H)
V
M
t
s
(L)
V
M
t
h
(L)
SF00191
SF00166
Waveform 3. Data Setup and Hold Times
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
MR
V
M
t
w
(L)
V
M
t
REC
V
M
CP
t
PHL
Qn
V
M
SF00158
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay and Master Reset to Clock recovery Time
TEST CIRCUIT AND WAVEFORMS
V
CC
NEGATIVE
PULSE
V
IN
PULSE
GENERATOR
R
T
D.U.T.
V
OUT
90%
V
M
10%
t
THL (
t
f
)
C
L
R
L
t
w
V
M
10%
t
TLH (
t
r
)
0V
90%
AMP (V)
t
TLH (
t
r
)
90%
POSITIVE
PULSE
V
M
10%
t
w
t
THL (
t
f
)
AMP (V)
90%
V
M
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude V
M
74F
3.0V
1.5V
rep. rate
1MHz
t
w
500ns
t
TLH
2.5ns
t
THL
2.5ns
SF00006
October 7, 1988
5
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