74F160A • 74F162A Synchronous Presettable BCD Decade Counter
April 1988
Revised July 1999
74F160A • 74F162A
Synchronous Presettable BCD Decade Counter
General Description
The 74F160A and 74F162A are high-speed synchronous
decade counters operating in the BCD (8421) sequence.
They are synchronously presettable for applications in pro-
grammable dividers. There are two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
synchronous multistage counters. The F160A has an asyn-
chronous Master Reset input that overrides all other inputs
and forces the outputs LOW. The F162A has a Synchro-
nous Reset input that overrides counting and parallel load-
ing and allows all outputs to be simultaneously reset on the
rising edge of the clock. The F160A and F162A are high
speed versions of the F160 and F162.
Features
s
Synchronous counting and loading
s
High-speed synchronous expansion
s
Typical count rate of 120 MHz
Ordering Code:
Order Number
74F160ASC
74F160ASJ
74F160APC
74F162ASC
74F162APC
Package Number
M16A
M16D
N16E
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F160A
74F162A
© 1999 Fairchild Semiconductor Corporation
DS009485
www.fairchildsemi.com
74F160A • 74F162A
Logic Symbols
74F160A
IEEE/IEC
74F162A
74F160A
74F162A
Unit Loading/Fan Out
U.L.
Pin Names
CEP
CET
CP
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
50/33.3
50/33.3
Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
20
µA/−0.6
mA
20
µA/−1.2
mA
20
µA/−0.6
mA
20
µA/−0.6
mA
20
µA/−1.2
mA
20
µA/−0.6
mA
20
µA/−1.2
mA
−1
mA/20 mA
−1
mA/20 mA
MR (74F160A) Asynchronous Master Reset Input (Active LOW)
SR (74F162A) Synchronous Reset Input (Active LOW)
P
0
–P
3
PE
Q
0
–Q
3
TC
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output
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2
74F160A • 74F162A
Functional Description
The 74F160A and 74F162A count modulo-10 in the BCD
(8421) sequence. From state 9 (HLLH) they increment to
state 0 (LLLL). The clock inputs of all flip-flops are driven in
parallel through a clock buffer. Thus all changes of the Q
outputs (except due to Master Reset of the (F160A) occur
as a result of, and synchronous with, the LOW-to-HIGH
transition of the CP input signal. The circuits have four fun-
damental modes of operation, in order of precedence:
asynchronous reset (F160A), synchronous reset (F162A),
parallel load, count-up and hold. Five control inputs—Mas-
ter Reset (MR, F160A), Synchronous Reset (SR, F162A),
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET)—determine the mode of oper-
ation, as shown in the Mode Select Table. A LOW signal on
MR overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on SR overrides counting and
parallel loading and allows all outputs to go LOW on the
next rising edge of CP. A LOW signal on PE overrides
counting and allows information on the Parallel Data (P
n
)
inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE and MR (F160A) or SR (F162A)
HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits
counting.
The F160A and F162A use D-type edge-triggered flip-flops
and changing the SR, PE, CEP and CET inputs when the
CP is in either state does not cause errors, provided that
the recommended setup and hold times, with respect to the
rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 9. To implement synchronous
multistage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the F568 data sheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers. In the F160A and F162A
decade counters, the TC output is fully decoded and can
only be HIGH in state 9. If a decade counter is preset to an
illegal state, or assumes an illegal state when power is
applied, it will return to the normal sequence within two
counts, as shown in the State Diagram.
Logic Equations:
Count Enable
=
CEP
×
CET
×
PE
TC
=
Q
0
×
Q
1
×
Q
2
×
Q
3
×
CET
Mode Select Table
*SR
L
H
H
H
H
PE
X
L
H
H
H
CET CEP
X
X
H
L
X
X
X
H
X
L
Action on the Rising
Clock Edge (
Reset (Clear)
Load (P
n
→
Q
n
)
Count (Increment)
No Change (Hold)
No Change (Hold)
)
State Diagram
*For 74’F162A only
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74F160A • 74F162A
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CC
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW
Current
Output Short-Circuit Current
Power Supply Current
−60
37
4.75
3.75
−0.6
−1.2
−150
55
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
mA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (CP, CEP,P
n
, MR (F160A))
V
IN
=
0.5V (CET, SR (F162A), PE)
V
OUT
=
0V
V
O
=
HIGH
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4
74F160A • 74F162A
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
Maximum Count Frequency
Propagation Delay, Count
CP to Q
n
(PE Input HIGH)
Propagation Delay, Load
CP to Q
n
(PE Input LOW)
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Propagation Delay
MR to Q
n
(74F160A)
Propagation Delay
MR to TC (74F160A)
4.5
8.0
10.5
4.5
12.5
4.5
11.5
ns
90
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
5.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
120
5.5
7.5
6.0
6.0
10.0
10.0
4.5
4.5
9.0
7.5
10.0
8.5
8.5
14.0
14.0
7.5
7.5
12.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
75
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
5.5
9.0
11.5
10.0
10.0
16.5
15.5
9.0
9.0
14.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
80
3.5
3.5
4.0
4.0
5.0
5.0
2.5
2.5
5.5
8.5
11.0
9.5
9.5
15.0
15.0
8.5
8.5
13.0
Max
MHz
ns
Units
ns
ns
ns
ns
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
P
n
to CP (74F160A)
Setup Time, HIGH or LOW
P
n
to CP (74F162A)
Hold Time, HIGH or LOW
P
n
to CP
Setup Time, HIGH or LOW
PE or SR to CP
Hold Time, HIGH or LOW
PE or SR to CP
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
Clock Pulse Width (Load)
HIGH or LOW
Clock Pulse Width (Count)
HIGH or LOW
MR Pulse Width, LOW
(74F160A)
Recovery Time
MR to CP (74F160A)
6.0
6.0
6.0
ns
4.0
5.0
5.0
5.0
2.0
2.0
11.0
8.5
2.0
0
11.0
5.0
0
0
5.0
5.0
4.0
6.0
5.0
2.5
2.5
13.5
10.5
2.0
0
13.0
6.0
0
0
5.0
5.0
5.0
8.0
5.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
5.5
5.5
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
4.0
5.0
5.0
5.0
2.0
2.0
11.5
9.5
2.0
0
11.5
5.0
0
0
5.0
5.0
4.0
7.0
5.0
ns
ns
ns
ns
ns
Max
ns
Units
5
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