Incorporates two enable inputs to simplify cascading and/or
data reception
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS139 - SMD 5962-96546
UT54ACTS139 - SMD 5962-96547
DESCRIPTION
The UT54ACS139 and the UT54ACTS139 are designed to be
used in high-performance memory-decoding or data-routing ap-
plications requiring very short propagation delay times.
The devices consist of two individual two-line to four-line de-
coders in a single package. The active-low enable input can be
used as a data line in demultiplexing applications.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
ENABLE
INPUTS
G
H
L
L
L
L
SELECT
INPUTS
B
X
L
L
H
H
A
X
L
H
L
H
Y0
H
L
H
H
H
OUTPUT
Y1
H
H
L
H
H
Y2
H
H
H
L
H
Y3
H
H
H
H
L
PINOUTS
16-Pin DIP
Top View
IG
1A
1B
1Y0
1Y1
1Y2
1Y3
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
2G
2A
2B
2Y0
2Y1
2Y2
2Y3
16-Lead Flatpack
Top View
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
2G
2A
2B
2Y0
2Y1
2Y2
2Y3
LOGIC DIAGRAM
(4)
1G
(1)
(5)
(6)
SELECT
1A
1B
(2)
(3)
(7)
(12)
2G
(15)
(11)
(10)
SELECT
2A
2B
(14)
(13)
(9)
1Y0
1Y1
1Y2
DATA
1Y3
2Y0
2Y1
2Y2
2Y3
1
LOGIC SYMBOL
1A
1B
1G
(2)
(3)
(1)
X/Y
1
2
EN
0
1
2
3
(4)
(5)
(6)
(7)
(12)
(11)
(10)
(9)
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
1A
1B
1G
(2)
(3)
(1)
DMUX
0
1
0
G
---
3
0
1
2
3
(4)
(5)
(6)
(7)
(12)
(11)
(10)
(9)
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
2A
2B
2G
(14)
(13)
(15)
2A
2B
2G
(14)
(13)
(15)
Note:
1. Logic symbols in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
3
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
I
OS
P
total
I
DDQ
ΔI
DDQ
Short-circuit output current
2 ,4
ACTS/ACS
Power dissipation
2, 8, ,9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100μA
I
OH
= -8.0mA
I
OH
= -100μA
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
V
O
= V
DD
and V
SS
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
15
15
pF
pF
-200
200
1.8
10
1.6
mA
mW/
MHz
μA
mA
-8
mA
.7V
DD
V
DD
- 0.25
8
.5V
DD
.7V
DD
-1
1
0.40
0.25
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
μA
V
V
OH
V
I
OL
mA
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose
≤
1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
FPGA/CPLD
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