INTEGRATED CIRCUITS
74F1244
Octal buffer (3-State)
Product specification
IC15 Data Handbook
1989 Apr 04
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal buffer (3-State)
74F1244
FEATURES
•
High impedance NPN base inputs for reduced loading
(20µA in High and Low states)
PIN CONFIGURATION
OEa 1
Ia0 2
Yb0 3
Ia1 4
Yb1 5
Ia2 6
Yb2 7
Ia3 8
Yb3 9
GND 10
20 V
CC
19 OEb
18 Ya0
17 Ib0
16 Ya1
15 Ib1
14 Ya2
13 Ib2
12 Ya3
11 Ib3
•
Low power, light loading
•
Functional pin-for-pin equivalent of 74F244
•
1/30th the bus loading of 74F244
•
Provides ideal interface and increase fan-out of MOS
microprocessors
•
Octal bus interface
•
3-State buffer outputs sink 64mA and source 15mA
DESCRIPTION
The 74F1244 is an octal buffer that is ideal for driving bus lines or
buffer memory address registers. The outputs are capable of sinking
64mA and sourcing up to 15mA, producing very good capacitive
drive characteristics. The device features two Output Enables, OEa
and OEb, each controlling four of the 3-State outputs.
The 74F1244 is pin and functionally compatible with the 74F244.
The lower power and light bus loading features make it an ideal part
to interface directly with MOS microprocessors.
TYPE
74F1244
SF00227
TYPICAL
PROPAGATION
DELAY
4.5ns
TYPICAL SUPPLY
CURRENT (TOTAL)
43mA
ORDERING INFORMATION
DESCRIPTION
20-pin plastic DIP
20-pin plastic SOL
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F1244N
N74F1244D
DRAWING
NUMBER
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
Ian, Ibn
OEa, OEb
Yan, Ybn
Data inputs
Output enable inputs (active Low)
Data outputs
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
750/106.7
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
15mA/64mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC SYMBOL
2
4
6
8
17
15
13
11
IEC/IEEE SYMBOL
1
19
EN1
EN2
18
16
14
12
2
3
5
7
9
Ia0
1
19
OEa
OEb
Ia1
Ia2
Ia3 Ib0
Ib1
Ib2
Ib3
2
4
6
8
1
Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3
17
15
18
V
CC
= Pin 20
GND = Pin 10
16
14
12
3
5
7
9
13
11
SF00228
SF01366
1989 Apr 04
2
853–0041 96221
Philips Semiconductors
Product specification
Octal buffer (3-State)
74F1244
LOGIC DIAGRAM
Ia0
2
18
Ya0
Ib0
17
3
Yb0
FUNCTION TABLE
INPUTS
OEa
L
Yb1
OUTPUTS
Ib
L
H
X
Ya
L
H
Z
Yb
L
H
Z
Ia
L
H
X
OEb
L
L
H
Ia1
4
16
Ya1
Ib1
15
5
L
Ia2
6
14
Ya2
Ib2
13
7
Yb2
H
H
L
X
Z
=
=
=
=
Ia3
8
12
Ya3
Ib3
11
9
Yb3
OEa
1
OEb
19
High voltage level
Low voltage level
Don’t care
High impedance “off” state
V
CC
= Pin 20
GND = Pin 10
SF00230
ABSOLUTE MAXIMUM RATINGS
(Operation
beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
128
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–15
64
+70
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
UNIT
1989 Apr 04
3
Philips Semiconductors
Product specification
Octal buffer (3-State)
74F1244
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
±10%
V
CC
±5%
V
CC
±10%
V
CC
±5%
V
CC
±10%
V
CC
±5%
V
CC
LIMITS
MIN
2.5
2.7
2.0
2.0
0.38
0.42
–0.73
0.55
0.55
–1.2
100
20
–20
50
–50
–100
30
V
CC
= MAX
57
43
–225
40
75
58
3.4
TYP
2
MAX
UNIT
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
mA
mA
mA
V
O
OH
High-level
High level output voltage
V
CC
= MIN,
V
IL
= MAX
MAX,
V
IH
= MIN
V
CC
= MIN,
V
IL
= MAX
MAX,
V
IH
= MIN
I
O
= –3mA
3mA
OH
I
O
= –15mA
15mA
OH
I
OL
= 48mA
I
OL
= 64mA
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Off-state output current,
High-level voltage applied
Off-state output current,
Low-level voltage applied
Short-circuit output current
3
I
CCH
Supply current (total)
I
CCL
I
CCZ
V
CC
= MIN, I
I
= I
IK
V
CC
= 0.0V, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
O
= 2.7V
V
CC
= MAX, V
O
= 0.5V
V
CC
= MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25°C
V
CC
= +5.0V
C
L
= 50pF, R
L
= 500Ω
MIN
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Ian, Ibn to Yn
Output Enable time
to High or Low level
Output Disable time
to High or Low level
Waveform 1
Waveform 2
Waveform 3
Waveform 2
Waveform 3
2.5
2.0
3.0
3.0
2.0
2.0
TYP
4.0
5.0
6.0
6.5
4.0
4.0
MAX
5.5
7.0
7.5
8.0
5.5
5.5
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
2.5
2.0
3.0
3.0
2.0
2.0
MAX
6.0
7.5
8.5
8.5
6.0
6.0
ns
ns
ns
ns
ns
ns
UNIT
1989 Apr 04
4
Philips Semiconductors
Product specification
Octal buffer (3-State)
74F1244
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
Ian, Ibn
V
M
V
M
t
PHL
OEn
V
M
t
PZL
V
M
t
PLZ
3.5V
t
PLH
Yn
V
M
V
M
Yn
V
M
V
OL
+0.3V
SF00234
SF00231
Waveform 1.
For Non-Inverting Outputs
Waveform 3. 3-State Output enable Time to Low Level and
Output Disable Time from Low Level
OEn
V
M
V
M
t
PZH
t
PHZ
V
OH
–0.3V
0V
Yn
V
M
SF00233
Waveform 2. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
TEST CIRCUIT AND WAVEFORMS
V
CC
7.0V
V
IN
PULSE
GENERATOR
R
T
D.U.T.
V
OUT
R
L
NEGATIVE
PULSE
90%
V
M
10%
t
THL (
t
f
)
C
L
R
L
t
TLH (
t
r
)
90%
POSITIVE
PULSE
10%
t
THL (
t
f
)
AMP (V)
90%
V
M
t
w
10%
0V
t
w
V
M
10%
t
TLH (
t
r
)
0V
AMP (V)
90%
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST
t
PLZ
t
PZL
All other
SWITCH
closed
closed
open
V
M
Input Pulse Definition
DEFINITIONS:
R
L
= Load resistor;
see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
family
amplitude V
M
74F
3.0V
1.5V
rep. rate
1MHz
t
w
500ns
t
TLH
2.5ns
t
THL
2.5ns
SF00777
1989 Apr 04
5
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