MM74C922 • MM74C923 16-Key Encoder • 20-Key Encoder
October 1987
Revised January 1999
MM74C922 • MM74C923
16-Key Encoder • 20-Key Encoder
General Description
The MM74C922 and MM74C923 CMOS key encoders pro-
vide all the necessary logic to fully encode an array of
SPST switches. The keyboard scan can be implemented
by either an external clock or external capacitor. These
encoders also have on-chip pull-up devices which permit
switches with up to 50 kΩ on resistance to be used. No
diodes in the switch array are needed to eliminate ghost
switches. The internal debounce circuit needs only a single
external capacitor and can be defeated by omitting the
capacitor. A Data Available output goes to a high level
when a valid keyboard entry has been made. The Data
Available output returns to a low level when the entered
key is released, even if another key is depressed. The Data
Available will return high to indicate acceptance of the new
key after a normal debounce period; this two-key roll-over
is provided between any two switches.
An internal register remembers the last key pressed even
after the key is released. The 3-STATE outputs provide for
easy expansion and bus operation and are LPTTL compat-
ible.
Features
s
50 kΩ maximum switch on resistance
s
On or off chip clock
s
On-chip row pull-up devices
s
2 key roll-over
s
Keybounce elimination with single capacitor
s
Last key register at outputs
s
3-STATE output LPTTL compatible
s
Wide supply range:
3V to 15V
s
Low power consumption
Ordering Code:
Order Number
MM74C922N
MM74C922WM
MM74C923WM
MM74C923N
Package Number
N18A
M20B
M20B
N20A
Package Description
18-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment for DIP
Pin Assignment for SOIC
Top View
MM74C922
Top View
MM94C922
© 1999 Fairchild Semiconductor Corporation
DS006037.prf
www.fairchildsemi.com
MM74C922 • MM74C923
Connection Diagrams
(Continued)
Pin Assignment for
DIP and SOIC Package
Top View
MM74C923
Truth Tables
(Pins 0 through 11)
Switch
Position
D
A
T
A
O
U
T
(Pins 12 through 19)
Switch
Position
D
A
T
A
O
U
T
Note 1:
Omit for MM74C922
0
1
2
3
4
5
6
7
8
9
10
11
Y1,X1 Y1,X2 Y1,X3 Y1,X4 Y2,X1 Y2,X2 Y2,X3 Y2,X4 Y3,X1 Y3,X2 Y3,X3 Y3,X4
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
1
0
1
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
1
0
1
0
A
B
C
D
E (Note 1)
12
Y4,X1
13
Y4,X2
14
Y4,X3
15
Y4,X4
16
17
18
19
Y5(Note 1), Y5 (Note 1), Y5 (Note 1), Y5 (Note 1),
X1
X2
X3
X4
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
1
1
0
0
1
A
B
C
D
E (Note 1)
0
0
1
1
0
1
0
1
1
0
0
1
1
1
0
1
1
1
1
0
www.fairchildsemi.com
2
MM74C922 • MM74C923
Block Diagram
3
www.fairchildsemi.com
MM74C922 • MM74C923
Absolute Maximum Ratings
(Note 2)
Voltage at Any Pin
Operating Temperature Range
MM74C922, MM74C923
Storage Temperature Range
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
700 mW
500 mW
−40°C
to
+85°C
−65°C
to
+150°C
V
CC
−
0.3V to V
CC
+
0.3V
Operating V
CC
Range
V
CC
Lead Temperature
(Soldering, 10 seconds)
3V to 15V
18V
260°C
Note 2:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise specified
Symbol
CMOS TO CMOS
V
T+
Positive-Going Threshold Voltage
at Osc and KBM Inputs
V
T−
Negative-Going Threshold Voltage
at Osc and KBM Inputs
V
IN(1)
Logical “1” Input Voltage,
Except Osc and KBM Inputs
V
IN(0)
Logical “0” Input Voltage,
Except Osc and KBM Inputs
I
rp
Row Pull-Up Current at Y1, Y2,
Y3, Y4 and Y5 Inputs
V
OUT(1)
Logical “1” Output Voltage
V
CC
=
5V, I
IN
≥
0.7 mA
V
CC
=
10V, I
IN
≥
1.4 mA
V
CC
=
15V, I
IN
≥
2.1 mA
V
CC
=
5V, I
IN
≥
0.7 mA
V
CC
=
10V, I
IN
≥
1.4 mA
V
CC
=
15V, I
IN
≥
2.1 mA
V
CC
=
5V
V
CC
=
10V
V
CC
=
15V
V
CC
=
5V
V
CC
=
10V
V
CC
=
15V
V
CC
=
5V, V
IN
=
0.1 V
CC
V
CC
=
10V
V
CC
=
15V
V
CC
=
5V, I
O
= −10 µA
V
CC
=
10V, I
O
= −10 µA
V
CC
=
15V, I
O
= −10 µA
V
OUT(0)
Logical “0” Output Voltage
V
CC
=
5V, I
O
=
10
µA
V
CC
=
10V, I
O
=
10
µA
V
CC
=
15V, I
O
=
10
µA
R
on
Column “ON” Resistance at
X1, X2, X3 and X4 Outputs
I
CC
Supply Current
Osc at 0V, (one Y low)
I
IN(1)
I
IN(0)
Logical “1” Input Current
at Output Enable
Logical “0” Input Current
at Output Enable
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
Except Osc and KBM Inputs
Except Osc and KBM Inputs
Logical “1” Output Voltage
V
CC
=
4.75V
V
CC
=
4.75V
I
O
= −360 µA
V
CC
=
4.75V
I
O
= −360 µA
V
OUT(0)
Logical “0” Output Voltage
I
O
= −360 µA
V
CC
=
4.75V
I
O
= −360 µA
0.4
V
2.4
V
V
CC
−
1.5
0.8
V
V
V
CC
=
15V, V
IN
=
0V
−1.0
−0.005
µA
V
CC
=
5V, V
O
=
0.5V
V
CC
=
10V, V
O
=
1V
V
CC
=
15V, V
O
=
1.5V
V
CC
=
5V
V
CC
=
10V
V
CC
=
15V
V
CC
=
15V, V
IN
=
15V
500
300
200
0.55
1.1
1.7
0.005
4.5
9
13.5
0.5
1
1.5
1400
700
500
1.1
1.9
2.6
1.0
3.0
6.0
9.0
0.7
1.4
2.1
3.5
8.0
12.5
3.6
6.8
10
1.4
3.2
5
4.5
9
13.5
0.5
1
1.5
−2
−10
−22
1.5
2
2.5
−5
−20
−45
4.3
8.6
12.9
2.0
4.0
6.0
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
V
V
V
V
V
V
Ω
Ω
Ω
mA
mA
mA
µA
Parameter
Conditions
Min
Typ
Max
Units
www.fairchildsemi.com
4
MM74C922 • MM74C923
DC Electrical Characteristics
Symbol
Parameter
(Continued)
Conditions
Min
Typ
Max
Units
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Output Source Current
(P-Channel)
Output Source Current
(P-Channel)
Output Sink Current
(N-Channel)
Output Sink Current
(N-Channel)
V
CC
=
5V, V
OUT
=
0V,
T
A
=
25°C
V
CC
=
10V, V
OUT
=
0V,
T
A
=
25°C
V
CC
=
5V, V
OUT
=
V
CC
,
T
A
=
25°C
V
CC
=
10V, V
OUT
=
V
CC
,
T
A
=
25°C
8
16
mA
1.75
3.6
mA
−8
−15
mA
−1.75
−3.3
mA
AC Electrical Characteristics
T
A
=
25°C, C
L
=
50 pF, unless otherwise noted
Symbol
t
pd0
, t
pd1
Parameter
Propagation Delay Time to
Logical “0” or Logical “1”
from D.A.
t
0H
, t
1H
Propagation Delay Time from
Logical “0” or Logical “1”
into High Impedance State
t
H0
, t
H1
Propagation Delay Time from
High Impedance State to a
Logical “0” or Logical “1”
C
IN
C
OUT
Input Capacitance
3-STATE Output Capacitance
(Note 3)
Conditions
Min
Typ
Max
Units
C
L
=
50 pF (Figure 1)
V
CC
=
5V
V
CC
=
10V
V
CC
=
15V
R
L
=
10k, C
L
=
10 pF (Figure 2)
V
CC
=
5V, R
L
=
10k
V
CC
=
10V, C
L
=
10 pF
V
CC
=
15V
R
L
=
10k, C
L
=
50 pF (Figure 2)
V
CC
=
5V, R
L
=
10k
V
CC
=
10V, C
L
=
50 pF
V
CC
=
15V
Any Input (Note 4)
Any Output (Note 4)
100
55
40
5
10
250
125
90
7.5
ns
ns
ns
pF
pF
80
65
50
200
150
110
ns
ns
ns
60
35
25
150
80
60
ns
ns
ns
Note 3:
AC Parameters are guaranteed by DC correlated testing.
Note 4:
Capacitance is guaranteed by periodic testing.
5
www.fairchildsemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
