REVISIONS
LTR
DESCRIPTION
Add QML-Q device type 03 with additional screening called out in
section 4. Low Temperature Operating Life (LTOL) test added to
section 4. Correction to section 1.3, remove paragraph 3.12. Added
oscillator test to Table I, also changed leakage current I
IN2
for F rad
hard devices from minimum of -20
μA
to -50
μA,
and a maximum of 5
μA,
to -50
μA.
Made changes to footnotes 1/ 3/, and 4/of Table I. ksr
Made changes to Table I Vol and V
OH
condition blocks, significant
change to I
CC
and I
CCIO
. Added a new footnote 5/ to Table I and
renumbered the rest of the original footnotes. Changed the A3
dimension on both packages X and Y. Removed figure 5. ksr
DATE (YR-MO-DA)
APPROVED
A
06-08-25
Raymond Monnin
B
08-02-08
Robert M. Heber
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
B
35
B
15
B
36
B
16
B
37
B
17
B
18
REV
SHEET
PREPARED BY
Kenneth Rice
CHECKED BY
Raj Pithadia
B
19
B
20
B
21
B
1
B
22
B
2
B
23
B
3
B
24
B
4
B
25
B
5
B
26
B
6
B
27
B
7
B
28
B
8
B
29
B
9
B
30
B
10
B
31
B
11
B
32
B
12
B
33
B
13
B
34
B
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
APPROVED BY
Raymond Monnin
DRAWING APPROVAL DATE
05-09-06
REVISION LEVEL
B
MICROCIRCUIT, MEMORY, DIGITAL, CMOS,
FIELD PROGRAMMABLE GATE ARRAY
(FPGA) 320K GATES with 24 dual-port SRAM
modules, RADIATION HARDENED,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
SHEET
67268
1 OF
37
5962-04229
DSCC FORM 2233
APR 97
5962-E184-08
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
|
|
|
Federal
stock class
designator
\
-
04229
|
|
|
RHA
designator
(see 1.2.1)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
Generic number 1/
UT6325
UT6325
Circuit function
320,000 gate CMOS FPGA
military temp range
320,000 gate CMOS FPGA
extended industrial temp range
320,000 gate CMOS FPGA
military temp range with
additional screening
Worse case
Delay Factor(K)
Max
Min
0.42
1.92
0.42
0.42
1.92
1.92 2/
01
|
|
|
Device
type
(see 1.2.2)
Q
|
|
|
Device
class
designator
(see 1.2.3)
X
|
|
|
Case
outline
(see 1.2.4)
C
|
|
|
Lead
finish
(see 1.2.5)
03
UT6325
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level
as follows:
Device class
M
Q or V
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class
level B microcircuits in accordance with MIL-PRF-38535, appendix A
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Z
Descriptive designator
See figure 1
See figure 1
See figure 1
Terminals
208
288
484
Package style
Quad flat package
Quad flat package
Ceramic land grid array
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
_______________
1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and
will also be listed in QML-38535 and MIL-HDBK-103 (see 6.6.2 herein).
2/ Device type 03 provides a QML-Q product with the additional testing as specified in section 4.2.2.d herein.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-04229
SHEET
B
2
1.3 Absolute maximum ratings. 2/
Supply voltage range (V
CCIO
) --------------------------------
Supply voltage range (V
CC
) ----------------------------------
Voltage on any pin ---------------------------------------------
Maximum power dissipation (P
D
)---------------------------
Lead temperature (soldering, 10 seconds) -------------
Thermal resistance, junction-to-case (θ
JC
):
Case outline X, Y, and Z------------------------------------
Junction temperature (T
J
) ------------------------------------
Storage temperature range ---------------------------------
1.4 Recommended operating conditions.
Case operating temperature Range(T
C
) devices 01, 03 -55°C to +125°C
device 02
-40°C to +125°C
Supply voltage relative to ground (V
CC
)-------------------
2.3 V to 2.7 V V
CC
, 3.0 V to 3.6 V V
CCIO
5/
Ground voltage (GND) ---------------------------------------
0 V dc
Input high voltage (V
IH
) ---------------------------------------
6/
Input low voltage (V
IL
) ----------------------------------------
6/
1.5 Radiation features.
4
Maximum total dose available (dose rate = 1 rads(Si)/s) .............................. 30.0 x 10 rads(Si)
Dose rate upset ............................................................................................
7/
Dose rate survivability...................................................................................
7/
Single event phenomenon (SEP) effective ...................................................
linear energy threshold (LET) with no upsets..............................................
7/
2
with no latch-up (maximum operating V
CC
and temperature) ...................... > 120 MeV-cm /mg
14
2
8/
Neutron irradiation ........................................................................................ 1 X 10 n/cm
-0.5 V dc to +4.6 V dc
-0.5 V dc to +3.6 V dc
-0.5 V dc to V
CCIO
+0.5 V
2.5 W 3/
+300°C
6° C/W
+150°C 4/
-65°C to +150°C
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 -
MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 -
MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at
http://assist.daps.dla.mil;quicksearch/
or
www.dodssp.daps.mil
or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
3/ Must withstand the added P
D
due to short circuit test (e.g., I
OS
).
4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
5/ For normal operation, user must maintain V
CCIO
≥
V
CC
+300mV.
6/ User configured I/O; may be LVTTL, LVCMOS3, or PCI.
7/ Contact the device manufacturer for detailed information.
8/ Guaranteed, but not tested.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-04229
SHEET
B
3
ELECTRONICS INDUSTRIES ALLIANCE (EIA)
JEDEC Standard EIA/JESD 78 -
IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201;
http://www.jedec.org.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute
the documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless
a specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outlines shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.4 Output load circuit. The output load and test circuit shall be as specified on figure 3.
3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required
in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535
and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or
for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-04229
SHEET
B
4
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 42 (see MIL-PRF-38535, appendix A).
3.11 Processing options. Since the device is capable of being programmed by either the manufacturer or the user to result
in a wide variety of configurations; two processing options are provided for selection in the contract, using an altered item
drawing.
3.11.1 Unprogrammed device delivered to the user. All testing shall be verified through group A testing as defined in 4.4.1
and table IIA. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program
configuration.
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
b.
Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)
electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
The test circuit shall be maintained by the manufacturer under document revision level control and shall be
made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015.
Use of built-in test circuitry testing the entire lot to verify programmability and AC performance without
programming the user array is an option the manufacturer may use.
(1)
c.
Dynamic burn-in for device class M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b
herein).
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-
PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
c.
d.
Interim and final electrical test parameters shall be as specified in table IIA herein.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
Additional screening for device type 03.
(1) 100% Internal visual, TM 2010 condition A
(2) 100% PIND (Single Pass)
(3) Serialization
(4) 100% X-ray (top view only)
(5) Group A
(6) Dynamic Burn-in, Delta, PDA (5%), for DC and functional test combined.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-04229
SHEET
B
5
FPGA/CPLD
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