Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
FEATURES
•
High speed parallel latches
•
5V I/O Compatible
•
Live insertion/extraction permitted
•
Extra data width for wide address/data paths or buses carrying
•
Power-up 3-State
•
Power-up reset
•
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
parity
DESCRIPTION
The 74ALVT16841 Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity. It is
designed for V
CC
operation at 2.5V or 3.3V with I/O compatibility to
5V.
The 74ALVT16841 consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
Bus-hold data inputs eliminate the need for external pull-up
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
resistors to hold unused inputs
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
Out
I
CCZ
PARAMETER
Propagation delay
nDx to nQx
Input capacitance DIR, OE
Output pin capacitance
Total supply current
C
L
= 50pF
V
I
= 0V or V
CC
V
I/O
= 0V or V
CC
Outputs disabled
CONDITIONS
T
amb
= 25°C
TYPICAL
UNIT
2.5V
1.8
2.1
3
9
40
3.3V
1.5
1.7
3
9
70
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVT16841 DL
74ALVT16841 DGG
NORTH AMERICA
AV16841 DL
AV16841 DGG
DWG NUMBER
SOT371-1
SOT364-1
1998 Feb 13
2
853-1868 18961
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
LOGIC SYMBOL
55
54
52
51
49
48
47
45
44
43
PIN CONFIGURATION
1OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1LE
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
V
CC
2D6
2D7
GND
2D8
2D9
2LE
1D0 1D1 1D2 1D3 1D4 1D5 1D6
56
1
1LE
1OE
1D7 1D8
1D9
1Q0
1Q1
GND
1Q2
1Q3
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2
42
3
41
5
40
6
38
8
37
9
36
10
34
12
33
13
31
14
30
V
CC
1Q4
1Q5
2D0 2D1 2D2 2D3 2D4 2D5 2D6
29
28
2LE
2OE
2D7 2D8
2D9
1Q6
GND
1Q7
1Q8
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
1Q9
2Q0
15
16
17
19
20
21
23
24
26
27
2Q1
SH00023
2Q2
GND
LOGIC SYMBOL (IEEE/IEC)
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
3D
4
∇
EN2
C1
EN4
C3
1D
2
∇
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
2Q3
2Q4
2Q5
V
CC
2Q6
2Q7
GND
2Q8
2Q9
2OE
SA00076
SA00077
1998 Feb 13
3
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49,
48, 47, 45, 44, 43
42, 41, 40, 38, 37,
36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10,
12, 13, 14
15, 16, 17, 19, 20,
21, 23, 24, 26, 27
1, 28
56, 29
4, 11, 18, 25, 32,
39, 46, 53
7, 22, 35, 50
SYMBOL
1D0 – 1D9
2D0 – 2D9
FUNCTION
FUNCTION TABLE
INPUTS
nOE
Data inputs
L
L
L
L
Data outputs
H
nLE
H
H
↓
↓
X
nDx
L
H
l
h
X
OUTPUTS
nQ0 – nQ9
L
H
L
H
Z
OPERATING MODE
Transparent
Latched
High impedance
1Q0 – 1Q9
2Q0 – 2Q9
1OE, 2OE
1LE, 2LE
GND
V
CC
Output enable inputs
(active-Low)
Latch enable inputs
(active rising edge)
Ground (0V)
Positive supply
voltage
L
L
X
NC
Hold
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low LE
transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low LE
transition
↓
= High-to-Low LE transition
NC= No change
X = Don’t care
Z = High impedance “off” state
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
D
D
D
D
D
D
D
D
D
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
SH00024
1998 Feb 13
4
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to 150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–1.2 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%; f
≥
1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
2.5V RANGE LIMITS
MIN
2.3
0
1.7
0.7
–8
8
24
10
+85
–40
MAX
2.7
5.5
3.3V RANGE LIMITS
MIN
3.0
0
2.0
0.8
–32
32
64
10
+85
MAX
3.6
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
1998 Feb 13
5
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