Philips Semiconductors Advanced BiCMOS Products
Application note
Thermal considerations for advanced logic
families (Futurebus+, ABT and MULTIBYTE)
AN241
INTRODUCTION
Thermal characteristics of integrated circuit
packages have been and increasingly will be
a major consideration to both producers and
users of electronics products. This is
because an increase in junction temperature
(T
J
) can adversely effect the long term
operating life of an IC. The advantages
realized by miniaturization often have
trade–offs in terms of increased junction
temperatures. Some of the variables affecting
T
J
are controlled by the IC manufacturer and
others are controlled by the system designer.
Depending on the environment in which the
IC is placed, the user could control well over
75% of the current that flows through the
device.
With the ever increasing use of Surface
Mount Device (SMD) technology,
management of thermal characteristics
becomes a growing concern because not
only are the SMD packages much smaller,
but the thermal energy is concentrated more
densely on the printed wiring board. For
these reasons, designers and manufacturers
of surface mount assemblies must be aware
of all the variables affecting T
J
.
There are five major factors controlled by the
user which contribute to increased BiCMOS
power dissipation.
1. Frequency of operation (output switching
frequency)
2. Input voltage levels
3. Output loading (capacitive and resistive)
4. V
CC
level
POWER DISSIPATION
Power dissipation for the ABT (Advanced
BiCMOS Technology), MULTIBYTE and
Futurebus+ devices can be estimated using
the same equation with the exception of
Futurebus+ transceivers. Due to BTL
OPEN–COLLECTOR outputs, BTL output
swings and the large current driven on the
BTL side (B side) of the transceivers the
equation must be altered.
2
3
4
5. Duty cycle
Each of these five factors are addressed in
the estimating equation except duty cycle.
Duty cycle can be addressed by “weighting”
terms 2, 5, 6, 7 and 8 appropriately.
Conditions under which measurements were
taken and upon which the Power Dissipation
Equation is based are:
1
s
P
D
+
V
CC
C
P
V
CC
i+1
F
OUT
i
)
V
CC
I
I
CCL
)
I
CCH
s
)
CCL
L
)
DI
CC
n
3
n
2n
5
s
6
h
)
(V
CC
*
V
OH
) (V
OH
*
V
OL
)
i+1
C
L
F
OUT
K
P
)
I
i
i
i+1
V
OH
R
D
i
7
s
l
8
(V
CC
*
V
OL
)
R
U
i
)
(V
OL
) (V
OH
*
V
OL
)
i+1
C
L
F
OUT
)
I
i
i+1
Power Dissipation Equation
V
CC
= 5V; 25°C; F
OUT
= 1, 10, 20, 30, 40,
and 50MHz; 50% duty cycle; C
L
= 0, 15, 50,
100, and 200pF; also 1, 2, 4, and 8 outputs
switching.
The first current term is due to I
CC
with the
device unloaded. It is caused by the internal
switching of the device.
s
C
P
V
CC
i+1
F
OUT
i
This term represents the I
CC
current with
absolutely no load. This measurement was
taken without the output pins connected to
the board. The C
P
for a device is calculated
by:
I (@50MHz)
*
I
CC
(@1MHz)
C
P
+
CC
V
CC
(49MHz)s
“s” is the number of outputs switching. C
P
will
be different for each product type.
The second term is current due to I
CC
with
the outputs unloaded. This I
CC
is caused by
switching the bipolar outputs.
(I
CCL
)
I
CCH
) s
2n
The I
CCL
and I
CCH
are the typical values
found in the corresponding product data
sheets. In the case of a 50% duty cycle an
average of I
CCL
and I
CCH
will flow through the
device. “n” is the number of outputs on the
device.
The third term is I
CCL
due to the outputs
being held Low. The I
CCH
current is in the
µA
range so if an output is held or forced High
then there is no appreciable I
CC
increase.
I
CCL
L
n
“L” is the number of outputs held Low.
The fourth term is through current due to
holding the CMOS inputs at 3.4V rather than
at the rail voltages. This term becomes
insignificant as load and frequency increase.
DI
CC
n
3
∆I
CC
is the through current when holding the
input High of a device to 3.4V. This value is
typically 300µA to 500µA. “n3” is the number
of inputs at 3.4V.
The fifth term is current through the upper
structure of the device. It is caused by the
external capacitive load and the output
June, 1992
1
Philips Semiconductors Advanced BiCMOS Products
Application note
Thermal considerations for advanced logic families
(Futurebus+, ABT and MULTIBYTE)
AN241
frequency. If a capacitive load exists then this
term can become very significant.
V
CC
I PATH
74ABT125
V
CC
6.0pF
6.5pF
7.0pF
7.0pF
4.5pF
5.5pF
7.0pF
11.0pF
11.0pF
9.0pF
8.5pF
11.0pF
11.5pF
11.5pF
11.5pF
9.0pF
16.0pF
17.0pF
6.0pF
7.5pF
9.0pF
9.5pF
7.0pF
7.5pF
11.0pF
16.0pF
16.0pF
74ABT126
74ABT240
74ABT240–1
74ABT244
I PATH
C
L
74ABT244–1
74ABT540
74ABT543
74ABT544
C
L
s
(V
OH
*
V
OL
)
S
i+1
C
L
F
OUT
i
74ABT620
i
(V
OH
*
V
OL
)
i+1
C
L
F
OUT
K
P
i
i
i
This current is not I
CC
, but rather current that
is “sinked” from an external source.
The eighth and final term is due to an
external load connected to V
CC
.
V
CC
I PATH
74ABT640
74ABT646
74ABT648
74ABT651
74ABT652
74ABT657
74ABT821
74ABT823
74ABT827
74ABT833
74ABT841
74ABT843
74ABT861
74ABT863
74ABT899
74ABT2952
74ABT2953
V
OH
–V
OL
is the voltage swing of the output.
C
L
is the output load (this can vary from
output to output). F
OUT
is the output
frequency which can also vary from output to
output.
K
P
is a factor which best estimates the
feedthrough current and variances in the
“V
OH
–V
OL
” factor as C
L
changes. K
P
= f(C
L
)
= –2.5E– 5C
L2
+4.3E–3C
L
+1.4 (C
L
is
expressed in unitless terms, e.g. “15” for
15pF…).
The sixth term is current through the upper
structure due to an external resistive load to
ground. This term includes both switching
outputs and static High outputs.
V
CC
I PATH
R
D
This term includes both switching and static
Low outputs.
I
i+1
(V
CC
*
V
OL
)
R
U
i
As with term seven, this is current that flows
through the lower structure of the IC. This
current too is not I
CC
.
R
D
THERMAL RESISTANCE
The ability of a package to conduct heat from
the chip to the environment is expressed in
terms of thermal resistance. The term
normally used is Theta JA (θ
JA
).
θ
JA
is often
separated into two components: thermal
resistance from the junction to case, and the
thermal resistance from the case to ambient.
θ
JA
represents the total resistance to heat
flow from the chip to ambient and is
expressed as follows:
θ
JC
+
θ
CA
=
θ
JA
Detailed
θ
JA
and
θ
JC
graphs will be included
in a later section of this note. For the ease of
the user a table with
θ
JA
and
θ
JC
values for
average die sizes is included here.
As the output frequency increases the
measured current approaches that of static
High outputs.
h
i+1
V
OH
R
D
i
R
D
is an external pull–down resistor. A
different value load could be applied to each
output.
The seventh current term is determined by
the output capacitive load and the output
frequency on the lower structure of the
device.
If this load exists then this term is also
significant.
All variables are the same as with the fifth
term with the exception that this is current
flowing through the lower structure of the IC.
Futurebus+ transceivers’ power dissipation
can be estimated in the same way as ABT
devices, excepting terms 3, 5, 6 and 8 in the
equation. An I
CCH
term needs to be added to
term 3. Term 3 would then read “I
CCL
L/n+
I
CCH
H/n”. “H” is the number of outputs held
static High. Since BTL outputs are
open–collector, terms 5 and 6 do not apply
and are discarded. Term 8 needs to be
adjusted—replace “(V
CC
–V
OL
)” with
“(2.1V–V
OL
)”. (If the level of the pull–up
voltage is not 2.1V then the actual pull–up
voltage would be substituted).
ABT C
P
VALUES
Many of the ABT products have been
characterized for their C
P
values. The
following table shows the products that have
been tested along with their corresponding
C
P
numbers. Over time C
P
for all ABT and
MULTIBYTE products will be characterized.
Refer to the individual product data sheets for
their values if the values are not noted below.
June, 1992
2
Philips Semiconductors Advanced BiCMOS Products
Application note
Thermal considerations for advanced logic families
(Futurebus+, ABT and MULTIBYTE)
θ
JA
AND
θ
JC
CALCULATIONS
FOR ABT, MULTIBYTE, AND
FUTUREBUS+
DIP
# Still 300
pins air lfpm
14
82
63
16
82
63
20
74
57
24
65
50
28
61
47
52
–
–
68
–
–
84
–
–
100
–
–
θ
JA
SO pkg PLCC/PQFP
Still 300 Still 300
air lfpm air lfpm
117
98
–
–
110
92
–
–
91
74
–
–
77
63
–
–
71
58
69
50
–
–
79
57
–
–
48
35
–
–
39
28
–
–
61
43
AN241
a diode to measure junction temperature. The
change in junction temperature can be
measured for a known power dissipation
which then allows for the thermal resistance
to be calculated using the expression shown
for
θ
JA
:
DT
J
(T
*
T
amb
)
+
J
P
D
P
D
package and the substrate, the number and
length of
traces
on the board,
thermally
conductive epoxies
, and
external cooling
.
PACKAGE CONSIDERATIONS
Following is a brief discussion on various
package factors and their effect on thermal
resistance. These items are inherent to the
package design, and therefore are fixed by
Signetics.
q
JA
+
where T
amb
is the temperature of the
ambient. For detailed information on the
measurement techniques and the tools used,
please refer to Signetics’ Reliability
Management Group Publication “IC Package
Thermal Resistance Characteristics”.
Once the value of
θ
JA
has been found then
T
J
can be calculated for varying P
D
s.
T
J
= P
D
× θ
JA
+ T
amb
For Signetics’ Futurebus+, ABT, and
MULTIBYTE the following criterion is used to
warn customers about excessive T
J
.
If the junction temperature (T
J
) could exceed
125°C but not 150°C then a warning to the
customer recommending thermal mounting
must appear on the data sheet.
If the T
J
could exceed 150°C but not 175°C
then it is necessary to warn the customer and
advise specific methods (to be found in the
product data sheet) to reduce the T
J
to
125°C. T
J
may be reduced either by thermal
mounting techniques or by the use of forced
air.
If T
J
could exceed 175°C then the product
release will not occur and a redesign will be
initiated or limit changes will be made in order
to lower the T
J
below the 175°C limit.
With the advent of multiple–byte products
(MULTIBYTE) it may become possible to
switch forty outputs simultaneously. When
this occurs the system designer must be
aware of the risks/dangers of rising T
J
values. Eventually compromises must be
made in order to keep T
J
below damaging
values.
Die size
has a large effect on thermal
resistance. Smaller die sizes result in higher
thermal resistances, given that other package
parameters remain constant. This effect is
reflected in the graphical data presented in
this note. Die size is a function of device type
and complexity.
Die attach methods
used by Signetics have
little effect on thermal resistance due to the
thinness (typically less than 1 mil), the good
thermal conductivity and the low power
dissipation of the ICs (typically less than 2
watts). Die attach methods and material can
have large effects on device reliability and die
stress. These items along with high thermal
conductivity control limit the selection of
materials and processes. The copper
leadframes of plastic packages require a
compliant die attach. To meet this
requirement, Signetics uses high thermal
conductivity adhesives.
Leadframe material
is one of the more
important factors. The higher the conductivity,
the lower the thermal resistance because of
the heat spreading effect of the leadframe.
For this reason all current Signetics plastic
packages use high thermal conductivity
copper alloy leadframes.
Leadframe design
is important especially for
plastic packages; large pad and pad support
structures improve thermal resistance.
Leadframe design is mainly controlled by die
size and pad position layout, however,
thermal dissipation is maximized whenever
possible.
Bond wires
, because of their small size, (1.0
to 1.3 mil diameter) do not provide a
significant thermal path in Signetics’
packages and thus have little effect on
thermal resistance.
Package body material
could have a large
effect on thermal resistance, but package
requirements such as reliability,
manufacturing, etc. control the selection of
these materials. Until new materials are
developed there is no real opportunity for
decreasing thermal resistance by increasing
package body thermal conductivity while
maintaining our high reliability standards.
Preliminary
θ
JA
(new packages)
SSOP
SQFP
#
Still 200
Still
pins
air lfpm
air
*20
143 119
–
*24
135 110
–
*100
–
–
68
# pins
14
16
20
24
28
52
68
84
100
DIP pkg
38
38
32
36
31
–
–
–
–
θ
JC
SO pkg
36
35
29
26
26
–
–
–
–
PLCC/PQFP
–
–
–
–
34
23
18
14
15
NOTES:
* Preliminary data only
•
(for ABT use 1.8mm
×
1.8mm (70mil
×
70mil) average die size)
•
(for MULTIBYTE and Futurebus+
transceivers use 3.0mm
×
3.5mm (118mil
×
138mil) average die size)
•
(for 68/84–pin Futurebus+ use 3.8mm
×
3.7mm (149mil
×
146mil) average die size)
•
(for 100–pin Futurebus+ use 6.0mm x
6.0mm (235mil
×
235mil) average die size)
FACTORS AFFECTING
θ
JA
There are several factors which affect the
thermal resistance of an IC package.
Effective thermal management demands a
sound understanding of these factors. Major
package variables include the
leadframe
design
and the
plastic
used to encapsulate
the device. Other variables such as the
die
size
and
die attach methods
also affect
thermal resistance. Other factors that have a
significant impact on the
θ
JA
include the
substrate
upon which the IC is mounted, the
layout density
, the
air–gap
between the
3
JUNCTION TEMPERATURE (T
J
)
Junction temperature (T
J
) is the temperature
of a powered IC at the substrate diode.
Signetics uses a technique known as the
temperature sensitive parameter (TSP)
method to measure the junction temperature
of an IC. This method uses the linear
relationship between forward voltage and
temperature (at a constant forward current) of
June, 1992
Philips Semiconductors Advanced BiCMOS Products
Application note
Thermal considerations for advanced logic families
(Futurebus+, ABT and MULTIBYTE)
AN241
THERMAL RESISTANCE
MEASUREMENTS
Thermal resistance values are presented as
a function of die size for each package. All
data was derived from tests carried out on
devices run at a constant power dissipation
(actual dissipation is given with each graph).
Whether power dissipation is higher or lower,
it will only slightly affect thermal resistance.
The general trend is for decreasing thermal
resistance with increasing power. This is
common to all packages.
Thermal resistance can be affected by slight
variation in internal leadframe design. For
example a larger die pad gives slightly lower
thermal resistance for the same size die. The
data presented represents the typical
Signetics leadframe/die combinations with
large die on large pads and small die on
small pads. There are many transition areas
where a die could be placed differently
depending on pad layout, aspect ratio, etc.
The effect of leadframe design is within the
±15%
accuracy of these graphs. Data is
available with improved accuracy (±7.5%).
For exact die/leadframe/power dissipation
combinations, contact Philips
Components–Signetics, Reliability
Management Group Publications, MS 35,
811 E. Arques Avenue, Sunnyvale, CA
94088–3409 or call (408) 991–2000.
Data is also available in the form of a
computer program (SIGTHERM) which runs
on IBM or compatible PCs in BASIC.
SIGTHERM provides estimates for
θ
JA
and
θ
JC
using exact die/leadframe/power
dissipation combinations resulting in more
accurate (±7.5%) data than in the graphs in
this note. SIGTHERM also gives
θ
JA
estimates at different air flow rates between
100–800 LFPM. The program requires the
user to input package type, die size, power
dissipation and leadframe code. Contact
Philips Components–Signetics Reliability
Management Group Publications, MS 35, for
more information on SIGTHERM.
EXAMPLE OF ABT T
J
CALCULATION
1. Calculate Current Consumption:
For example the ABT244’s C
P
is 4.5pF. Let
V
CC
= 5V; operating temperature = 25°C;
F
OUT
= 50MHz for 4 outputs switching; hold 2
inputs Low and 2 inputs High (at 3.4V); C
L
=
100pF; 500Ω pull–down; no pull–up.
1
4
When calculating the total power dissipation
of the device, the first four terms are
multiplied by V
CC
, which in this example is
5V.
5V(17.625mA) = 88.1mW
The fifth and sixth terms are multiplied by the
voltage drop across the upper structure of the
device, V
CC
–V
OH
. This is approximately 1V.
1V(168.1mA) = 168.1mW
4.5pF
5V
i+1
50MHz
+
4.5mA
+
2
3
4
24mA
)
0.5mA 4
)
24mA 2
)
.5mA(2)
8
2(8)
+
6.125mA
)
6mA
)
1mA
+
13.125mA
These unloaded terms contribute only 9% of
the total I
CC
current.
+
5
4
6
The seventh and eighth terms are multiplied
by the voltage drop across the lower
structure of the device, V
OL
.
0.2V(76mA) = 15.2mW
The total estimated power dissipation of an
ABT244 with 4 outputs switching, at 25°C,
with V
CC
= 5V, with 2 outputs held static Low,
and 2 inputs at 3.4V, with 100pF capacitive
loads, 500Ω pull–downs, and 50MHz
switching frequency is:
271.4mW
3. Determine
θ
JA
The
θ
JA
for a 20–pin SOL package using the
average die size for ABT is 91°C/W @ 0.7W.
4. Determine
θ
JA
@ 271mW P
D
6
4V
500W
(4V
*
0.2V)
i+1
100pF50MHz1.58
)
i+1
Using the AVERAGE EFFECT of POWER
DISSIPATION on
θ
JA
graph calculate the
In this example terms five and six contribute
percentage change in power = (.271W –
over 90% of the total I
CC
current . This part of
.7W)/.7W = –.61 (–61% change) then check
I
CC
is entirely due to external loading.
the graph and see that
θ
JA
increases by
7
8
8.5%. So
θ
JA
increases to 91 + 91
×
.085 =
6
4
(5V
*
02V)
98.7°C/W.
100pF50MHz
)
(4V
*
0.2V)
R
i+1
i+1
5. Assume 200 LFPM Air Flow
+
76mA
)
0
+
76mA
Calculate the effects of air flow by referring to
These terms are not I
CC
currents, but rather
the graph AVERAGE EFFECT of AIR FLOW
currents “sinked” by the lower structure of the
on
θ
JA
. The
θ
JA
is decreased by 14% leaving
device.
a
θ
JA
of 98.7 – (.14
×
98.7) = 84.9°C/W.
Term
1&2
3
4
5
Predicted
10.63mA
6mA
1mA
120.1mA
48mA
76mA
0mA
185.7mA
Measured
10.2mA
6mA
1.5mA
117.8mA
53mA
––
––
188.4mA
6. Final Calculations for T
J
for the ABT244
T
J
= (P
D
× θ
JA
) + T
amb
= (.271W
×
84.9°C/W)
+ 70°C = 93°C. Referring to the warnings in
the JUNCTION TEMPERATURE section, a
93°C T
J
would constitute absolutely no
junction temperature worries.
where: K
P
= –2.5E–5(100
2
) + 4.3E–3(100) +
1.4 = 1.58
EXAMPLES OF THERMAL
CALCULATIONS
Junction temperature can be estimated using
the following equation:
T
J
= (θ
JA
×
P
D
) + T
amb
Where:
T
J
= Junction Temperature (°C)
θ
JA
= Thermal Resistance
Junction–to–Ambient
P
D
= Power Dissipation at a T
J
T
amb
= Temperature of Ambient (°C)
June, 1992
6
7
8
Total 1–6
For this example the equation estimate is
within 1% of the actual I
CC
current!! This is
not a claim of 1% accuracy, but the equation
is quite accurate. (Terms 7 and 8 are not
included in the comparison.)
2. Finding P
D
(V
×
I)
4
Philips Semiconductors Advanced BiCMOS Products
Application note
Thermal considerations for advanced logic families
(Futurebus+, ABT and MULTIBYTE)
AN241
EXAMPLE OF FUTUREBUS+
TRANSCEIVER T
J
FOR BTL SIDE
(”A” side can be treated like ABT)
1. Calculate Current Consumption
For example let the FB2031’s C
P
be 16pF.
Let V
CC
= 5V; operating temperature = 25°C;
F
OUT
= 50MHz for 5 outputs switching; hold 2
inputs Low and 2 inputs High (at 3.4V); C
L
=
100pF; no pull–down; 16.5Ω pull–up.
1
16pF(5V(5)50MHz) = 20mA
+
2
(17mA + 17mA)/2(9)
×
5 = 9.44mA
+
3
17mA/9
×
2 + 17mA/9
×
2 = 15.1mA
+
4
.5mA
×
2 = 1mA
+
7
1.1V(5)100pF50MHz = 27.5mA
+
8
7(2.1V–1.0V)/16.5Ω = 466.7mA
2. Finding P
D
(V
×
I)
The first four current terms are multiplied by
V
CC
.
5V(20mA + 9.44mA + 15.1mA + 1mA) =
227.7mW
Term seven is multiplied by 1V (V
OL
).
1V(27.5mA) = 27.5mW
Term eight is also multiplied 1V (V
OL
).
1V(466.7mA) = 466.7mW
The total estimated power dissipation of an
FB2031 with 5 outputs switching, at 25°C,
with V
CC
= 5V, with 2 outputs held static Low,
and 2 inputs at 3.4V, with 100pF capacitive
loads, no pull–downs, 16.5Ω pull–ups and
50MHz switching frequency is:
227.7 + 27.5 + 466.7 = 721.9mW
Term eight contributed over 65% of the power
dissipated by the FB2031 in this example.
The power dissipated by the IC with no
external loading totals only 32% of the power.
3. Determine
θ
JA
The FB2031 is packaged in the 52–pin
PQFP. Using an average die size of 118
×
138 yields a
θ
JA
of 79°C/W @ 1W power
dissipation (see
θ
JA
graph).
4. Determine
θ
JA
@ 721.9mW P
D
Using the AVERAGE EFFECT of POWER
DISSIPATION on
θ
JA
graph calculate the
percentage change in power = (0.7219W –
1W)/1W = –.28 (–28% change) then check
the graph and see that
θ
JA
increases by
3.4%. So
θ
JA
increases to 79 + 79
×
.034 =
81.7°C/W.
5. Assume 200 LFPM Air Flow
Calculate the effects of air flow by referring to
the graph AVERAGE EFFECT of AIR FLOW
on
θ
JA
. The
θ
JA
is decreased by 22.5%
leaving a
θ
JA
of 81.7 – (.225
×
81.7) =
63.3°C/W.
6. Final Calculations for T
J
for the FB2031
T
J
= (P
D
× θ
JA
) + T
amb
= (0.7219W
×
63.3°C/W) + 70°C = 115.1°C. Referring to the
warnings in the JUNCTION TEMPERATURE
section, a 115.1°C T
J
would constitute no
temperature worries.
MODIFYING
θ
JA
FOR POWER DISSIPATION AND AIRFLOW
10
8
6
4
–15
2
%
Change
in
θ
JA
0
–2
–30
–4
–6
–8
–10
–60
–40
–20
0
20
40
60
80
100
120
% Change in Power Dissipation
–35
–40
–45
0
100
200
300
400
500
600
700
800
900 1000
% Change in Power Dissipation
–20
%
Change
in
θ
JA
–25
S
O
SOL
DIP
PLCC,
PQFP
TEST POWER
RANGE
.3 TO 3 WATTS
0
–5
–10
SO Philips PCB(1.12”
×
0.75”
×
0.059”)
SOL Philips PCB(1.58”
×
0.75”
×
0.059”)
PLCC & PQFP Signetics PCB(2.24”
×
2.24”
×
0.062””)
DIP Textool ZIF Socket with 0.040”
Stand–off
Average Effect of Power Dissipation on
θ
JA
Average Effect of Air Flow on
θ
JA
June, 1992
5
Microchip MCU
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