INTEGRATED CIRCUITS
74ALVT16260
12-bit to 24-bit multiplexed D-type latches
(3-State)
Product specification
IC23 Data Handbook
1998 Jan 30
Philips
Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
FEATURES
•
ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model
DESCRIPTION
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used
in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications
include multiplexing and/or demultiplexing of address and data
information in microprocessor or bus-interface applications. This
device is alto useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V
CC
through a pull-up resistor;
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline
Package (SSOP) and 56-pin Thin Shrink Small Outline Package
(TSSOP).
•
Latch-up protection exceeds 500mA per JEDEC Standard
JESD-17.
•
Distributed V
CC
and GND pin configuration minimizes high-speed
switching noise.
•
Output capability (–32mA I
OH
, 64mA I
OL
).
•
Bus hold inputs eliminate the need for external pull-up resistors.
•
5V I/O compatible
•
Live insertion/extraction permitted
•
Power-up 3-State
•
Power-up Reset
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
nAx to nBx
nBx to nAx
C
L
= 50 pF
V
I
= 0 V or V
CC
V
I/O
= 0 V or 5.0 V
Outputs disabled
CONDITIONS
T
amb
= 25°C; GND = 0V
TYPICAL
2.5V
3.5
3.3
4
9
100
3.3V
2.8
2.6
4
9
80
ns
pF
pF
µA
UNIT
Input capacitance
Output capacitance
Total supply current
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVT16260 DL
74ALVT16260 DGG
NORTH AMERICA
AV16260 DL
AV16260 DGG
DWG NUMBER
SOT371-1
SOT364-1
1998 Jan 30
2
853-2046-18918
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
PIN DESCRIPTION
PIN NUMBER
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43
1, 29, 56
2, 27, 30, 55
28
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
An
1Bn
2Bn
OEA, OE1B, OE2B
LE1B, LE2B, LEA1B, LEA2B
SEL
GND
V
CC
FUNCTION
Data inputs/outputs (A)
Data inputs/outputs (B1)
Data inputs/outputs (B2)
Output enable input (active low)
Latch enable inputs
B1/B2 input select input
Ground (0V)
Positive supply voltage
PIN CONFIGURATION
OEA
LE1B
2B3
GND
2B2
2B1
V
CC
A1
A2
1
2
3
4
5
6
7
8
9
56 OE2B
55 LEA2B
54 2B4
53 GND
52 2B5
51 2B6
50 V
CC
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
35 V
CC
34 1B6
33 1B5
32 GND
31 1B4
30 LEA1B
29 OE1B
FUNCTION TABLES
B to A (OEB = H)
INPUTS
1B
H
L
X
X
X
X
X
2B
X
X
X
H
L
X
X
SEL
H
H
H
L
L
L
X
LE1B
H
H
L
X
X
X
X
LE2B
X
X
X
H
H
L
X
OEA
L
L
L
L
L
L
H
OUTPUT
A
H
L
A0
H
L
A0
Z
A3 10
GND 11
A4 12
A5 13
A6 14
A7 15
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
V
CC
22
1B1 23
1B2 24
GND 25
1B3 26
LE2B 27
SEL 28
A to B (OEA = H)
INPUTS
A
H
L
H
L
H
L
X
X
X
X
X
LEA1B
H
H
H
H
L
L
L
X
X
X
X
LEA2B
H
H
L
L
H
H
L
X
X
X
X
OE1B
L
L
L
L
L
L
L
H
L
H
L
OE2B
L
L
L
L
L
L
L
H
H
L
L
OUTPUT
1B
H
L
H
L
1B0
1B0
1B0
Z
Active
Z
Active
2B
H
L
2B0
2B0
H
L
2B0
Z
Z
Active
Active
SA00435
1998 Jan 30
3
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
LOGIC DIAGRAM (POSITIVE LOGIC)
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
2
27
30
55
56
29
1
28
C1
G1
A1
8
1
1
1D
23
1B1
C1
1D
6
2B1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
SA00436
1998 Jan 30
4
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to +150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%; f
≥
1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
2.5V RANGE LIMITS
MIN
2.3
0
1.7
0.7
–8
8
24
10
+85
–40
MAX
2.7
5.5
3.3V RANGE LIMITS
MIN
3.0
0
2.0
0.8
–32
32
64
10
+85
MAX
3.6
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
1998 Jan 30
5
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