INTEGRATED CIRCUITS
74LV174
Hex D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Apr 07
IC24 Data Handbook
1998 May 20
Philips
Semiconductors
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive edge-trigger
74LV174
FEATURES
•
Wide operating voltage: 1.0 to 5.5V
•
Optimized for Low Voltage applications: 1.0 to 3.6V
•
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
•
Typical V
OLP
(output ground bounce)
t
0.8V @ V
CC
= 3.3V,
•
Typical V
OHV
(output V
OH
undershoot)
u
2V @ V
CC
= 3.3V,
•
Output capability: standard
•
I
CC
category: MSI
T
amb
= 25°C
T
amb
= 25°C
DESCRIPTION
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
set–up time prior to the LOW–to–HIGH clock transition, is
transferred to the corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently
of clock or data inputs.
The device is useful for applications requiring true outputs only and
clock and master reset inputs that are common to all storage
elements.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
v2.5
ns
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
PD
PARAMETER
Propagation delay
CP to Q
n
MR to Q
n
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
V
CC
= 3.3V
Notes 1 and 2
CONDITIONS
C
L
= 15pF
V
CC
= 3.3V
TYPICAL
16
13
77
3.5
17
UNIT
ns
MHz
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
V
CC2
x f
i
)S
(C
L
V
CC2
f
o
) where:
P
D
= C
PD
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
V
CC2
f
o
) = sum of the outputs.
S
(C
L
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV174 N
74LV174 D
74LV174 DB
74LV174 PW
NORTH AMERICA
74LV174 N
74LV174 D
74LV174 DB
74LV174PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
1998 May 20
2
853–1964 19422
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive edge-trigger
74LV174
PIN CONFIGURATION
LOGIC SYMBOL
9
MR
Q
0
D
0
D
1
Q
1
D
2
Q
2
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q
5
D
5
D
4
Q
4
D
3
Q
3
CP
CP
3
4
6
11
13
14
D
0
D
1
D
2
D
3
D
4
D
5
MR
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
2
5
7
10
12
15
1
SV00347
SV00348
PIN DESCRIPTION
PIN
NUMBER
1
2, 5, 7, 10,
12, 15
3, 4, 6, 11,
13, 14
8
9
16
SYMBOL
MR
Q
0
to Q
5
D
0
to D
5
GND
CP
V
CC
FUNCTION
Asynchronous master reset (active
LOW)
Flip-flop outputs
Data inputs
Ground (0V)
Clock input (LOW-to-HIGH, edge-
triggered)
Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
9
1
C1
R
3
4
6
11
13
14
1D
2
5
7
10
12
15
SV00349
1998 May 20
3
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive edge-trigger
74LV174
FUNCTIONAL DIAGRAM
FUNCTION TABLE
INPUTS
OPERATING MODES
Reset (clear)
MR
L
H
H
CP
X
↑
↑
D
n
X
h
l
OUTPUTS
Q
0
L
H
L
3
4
6
11
13
14
D
0
D
1
D
2
D
3
D
4
D
5
FF1
to
FF6
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
2
5
7
10
12
15
Load ‘1’
Load ‘0’
H
h
L
l
q
↑
= HIGH voltage level
= HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
= LOW voltage level
= LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
= Lower case letter indicates the state of referenced input
one set-up time prior to the LOW-to-HIGH CP transition
= LOW–to–HIGH clock transition
1
9
MR
CP
SV00350
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
Input voltage
Output voltage
Operating ambient temperature range in free
air
Input rise and fall times
See DC and AC
characteristics
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
PARAMETER
DC supply voltage
CONDITIONS
See Note1
MIN
1.0
0
0
–40
–40
–
–
–
–
–
–
–
TYP.
3.3
–
–
MAX
5.5
V
CC
V
CC
+85
+125
500
200
100
50
UNIT
V
V
V
°C
t
r
, t
f
ns/V
NOTES:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
1998 May 20
4
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive edge-trigger
74LV174
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
,
±I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– standard outputs
DC V
CC
or GND current for types with
–standard outputs
Storage temperature range
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
–0.5V < V
O
< V
CC
+ 0.5V
CONDITIONS
RATING
–0.5 to +7.0
20
50
25
50
–65 to +150
750
500
400
UNIT
V
mA
mA
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
V
CC
= 1.2V
V
IH
HIGH level Input
voltage
V
CC
= 2.0V
V
CC
= 2.7 to 3.6V
V
CC
= 4.5 to 5.5V
V
CC
= 1.2V
V
IL
LOW level Input
voltage
V
CC
= 2.0V
V
CC
= 2.7 to 3.6V
V
CC
= 4.5 to 5.5
V
CC
= 1.2V; V
I
= V
IH
or V
IL;
–I
O
= 100µA
HIGH level output
voltage all outputs
out uts
voltage;
V
OH
HIGH level output
voltage;
g
STANDARD
outputs
V
CC
= 2.0V; V
I
= V
IH
or V
IL;
–I
O
= 100µA
V
CC
= 2.7V; V
I
= V
IH
or V
IL;
–I
O
= 100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
–I
O
= 100µA
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
–I
O
= 100µA
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
–I
O
= 6mA
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
–I
O
= 12mA
V
CC
= 1.2V; V
I
= V
IH
or V
IL;
I
O
= 100µA
V
CC
= 2.0V; V
I
= V
IH
or V
IL;
I
O
= 100µA
V
CC
= 2.7V; V
I
= V
IH
or V
IL;
I
O
= 100µA
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 100µA
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 100µA
LOW level output
voltage;
g
STANDARD
outputs
V
CC
= 3.0V;V
I
= V
IH
or V
IL;
I
O
= 6mA
V
CC
= 4.5V;V
I
= V
IH
or V
IL;
I
O
= 12mA
1.8
2.5
2.8
4.3
2.40
3.60
1.2
2.0
2.7
3.0
4.5
2.82
4.20
0
0
0
0
0
0.25
0.35
0.2
0.2
0.2
0.2
0.40
0.55
0.2
0.2
0.2
0.2
0.50
V
0.65
V
1.8
2.5
2.8
4.3
2.20
V
3.50
V
0.9
1.4
2.0
0.7*V
CC
0.3
0.6
0.8
0.3*V
CC
-40°C to +85°C
TYP
1
MAX
-40°C to +125°C
MIN
0.9
1.4
2.0
0.7*V
CC
0.3
0.6
0.8
0.3*V
CC
V
V
MAX
UNIT
LOW level output
voltage
out uts
voltage; all outputs
V
OL
1998 May 20
5
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
