Philips Semiconductors
Product specification
16-bit bus transceiver/register (3-State)
74ALVCH16646
FEATURES
•
Complies with JEDEC standard no. 8-1A
•
CMOS low power consumption
•
MULTIBYTE
TM
flow-through pin-out architecture
•
Low inductance, multiple V
CC
and ground pins for minimum noise
and ground bounce
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
PIN CONFIGURATION
1DIR 1
1CP
AB
2
1S
AB
3
GND 4
1A0 5
1A1 6
V
CC
7
1A2 8
1A3 9
56 1OE
55 1CP
BA
54 1S
BA
53 GND
52 1B0
51 1B1
50 V
CC
49 1B2
48 1B3
47 1B4
46 GND
45 1B5
44 1B6
43 1B7
42 2B0
41 2B1
40 2B2
39 GND
38 2B3
37 2B4
36 2B5
35 V
CC
34 2B6
33 2B7
32 GND
31 2S
BA
30 2CP
BA
29 2OE
•
Direct interface with TTL levels
•
Current drive
±
24 mA at 3.0 V
•
Output drive capability 50Ω transmission lines @ 85°C
•
All inputs have bushold circuitry
DESCRIPTION
The 74ALVCH16646 consists of 16 non-inverting bus transceiver
circuits with 3-State outputs, D-type flip-flops and control circuitry
arranged for multiplexed transmission of data directly from the
internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the
internal registers, as the appropriate clock (CP
AB
or CP
BA
) goes to a
HIGH logic level. Output enable (OE) and direction (DIR) inputs are
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
‘A’ or ‘B’ register, or in both. The select source inputs (S
AB
and S
BA
)
can multiplex stored and real-time (transparent mode) data. The
direction (DIR) input determines which bus will receive data when
OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’ data
may be stored in the ‘B’ register and/or ‘B’ data may be stored in the
‘A’ register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, ‘A’ or ‘B’ may be driven at a time.
To ensure the high impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
1A4 10
GND 11
1A5 12
1A6 13
1A7 14
2A0 15
2A1 16
2A2 17
GND 18
2A3 19
2A4 20
2A5 21
V
CC
22
2A6 23
2A7 24
GND 25
2S
AB
26
2CP
AB
27
2DIR 28
SY00011
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
≤
2.5ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
F
max
PARAMETER
Propagation delay
nAx to nBx
Input capacitance
Power dissipation capacitance per channel
Maximum clock frequency
V
I
= GND to V
CC1
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
Outputs enabled
Outputs disabled
CONDITIONS
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
TYPICAL
2.6
2.7
3.0
36
4
300
320
UNIT
ns
pF
pF
MHz
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16646 DGG
NORTH AMERICA
ACH16646 DGG
DWG NUMBER
SOT364-1
1998 Sep 03
2
853-2116 19959
Philips Semiconductors
Product specification
16-bit bus transceiver/register (3-State)
74ALVCH16646
LOGIC DIAGRAM (one section)
OE
DIR
S
BA
CP
BA
S
AB
CP
AB
V
CC
S
Y
An
D
1
D
2
Q
FF
n
CP
D
MUX
V
CC
S
D
1
D
FF
n
CP
8 IDENTICAL CHANNELS
Q
D
2
Y
Bn
MUX
SY00012
FUNCTION TABLE
INPUTS
nOE
X
X
H
H
L
L
L
L
*
un
H
L
X
↑
nDIR
X
X
X
X
L
L
nCP
AB
↑
X
↑
H or L
X
X
nCP
BA
X
↑
↑
H or L
X
H or L
nS
AB
X
X
X
X
X
X
nS
BA
X
X
X
X
L
H
input
un*
input
output
DATA I/O *
nAx
nBx
un*
input
input
input
FUNCTION
store A, B unspecified*
store B, A unspecified*
store A and B data, isolation
hold storage
real-time B data to A bus
stored B data to A bus
H
X
X
L
X
real-time A data to B bus
input
output
H
H or L
X
H
X
stored A data to B bus
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled,
i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs.
= unspecified
= HIGH voltage level
= LOW voltage level
= don’t care
= LOW-to-HIGH level transition
1998 Sep 03
4
Philips Semiconductors
Product specification
16-bit bus transceiver/register (3-State)
74ALVCH16646
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
DC Input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
CONDITIONS
MIN
2.3
3.0
0
0
–40
0
0
MAX
2.7
V
3.6
V
CC
V
CC
+85
20
10
V
V
°C
ns/V
UNIT
V
I
V
O
T
amb
t
r
, t
f
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC in ut voltage
input
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 11.3 mW/K
above +55°C derate linearly with 8 mW/K
V
I
t0
For control pins
1
For data inputs
1
V
O
uV
CC
or V
O
t
0
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +4.6
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
850
600
V
mA
V
mA
mA
°C
mW
UNIT
V
mA
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Sep 03
5
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