Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16501
FEATURES
•
Complies with JEDEC standard no. 8-1A.
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Current drive
±
24 mA at 3.0 V
•
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched or clocked mode.
DESCRIPTION
The 74ALVCH16501 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
AB
and OE
BA
), latch enable (LE
AB
and LE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates
in the transparent mode when LE
AB
is High. When LE
AB
is Low, the
A data is latched if CP
AB
is held at a High or Low logic level. If LE
AB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
AB
. When OE
AB
is High, the outputs are
active. When OE
AB
is Low, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
. The output enables are complimentary (OE
AB
is active
High, and OE
BA
is active Low).
To ensure the high impedance state during power up or power
down, OE
BA
should be tied to V
CC
through a pullup resistor and
OE
AB
should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
•
All inputs have bushold circuitry
•
Output drive capability 50Ω transmission lines @ 85°C
•
3-State non-inverting outputs for bus oriented applications
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
= 2.5ns
SYMBOL
t
PHL
/t
PLH
C
I/O
C
I
C
PD
PARAMETER
Propagation delay
An, Bn to Bn, An
Input/output capacitance
Input capacitance
Power dissipation capacitance per
latch
V
I
= GND to V
CC1
Outputs enabled
Outputs disabled
CONDITIONS
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
TYPICAL
2.8
3.0
8.0
4.0
21
3
UNIT
ns
pF
pF
pF
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16501 DGG
DWG NUMBER
SOT364-1
1998 Sep 29
2
853–2091 20106
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16501
FUNCTION TABLE
INPUTS
OEAB
L
H
H
H
H
H
H
H
H
LEAB
X
H
H
↓
↓
L
L
L
L
CPAB
X
X
X
X
X
↑
↑
H or L
H or L
An
X
H
L
h
I
h
I
X
X
OUTPUTS
Bn
Z
H
L
H
L
H
L
H
L
Disabled
Trans arent
Transparent
Latch data & dis lay
display
Clock data & display
dis lay
Hold data & display
dis lay
OPERATING MODE
NOTE:
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
H = High voltage level
h = High voltage level one set-up time prior to the Enable or Clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Enable or Clock transition
NC= No Change
X = Don’t care
Z = High Impedance ”off” state
↓
= High-to-Low Enable or Clock transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
DC Input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
CONDITIONS
LIMITS
MIN
2.3
3.0
0
0
–40
0
0
MAX
2.7
V
3.6
V
CC
V
CC
+85
20
10
V
V
°C
ns/V
UNIT
V
CC
V
I
V
O
T
amb
t
r
, t
f
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC in ut voltage
input
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 8 mW/K
V
I
t0
For control pins
1
For data inputs
1
V
O
uV
CC
or V
O
t
0
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +4.6
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
600
V
mA
V
mA
mA
°C
mW
UNIT
V
mA
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Sep 29
5
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