74ALVCF162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in
Outputs
September 2001
Revised October 2001
74ALVCF162835
Low Voltage 18-Bit Universal Bus Driver with 3.6V
Tolerant Outputs and 26
Ω
Series Resistors in Outputs
General Description
The 74ALVCF162835 low voltage 18-bit universal bus
driver combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Outputs (O
n
) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74ALVCF162835 is designed with 26
Ω
series resistors
in the outputs. This design reduces noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
The 74ALVCF162835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVCF162835 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
I
Compatible with PC133 DIMM module specifications
I
1.65V-3.6V V
CC
specifications provided
I
3.6V tolerant outputs
I
26
Ω
series resistors in outputs
I
t
PD
(CLK to O
n
)
3.7 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
7.4 ns max for 1.65V to 1.95V V
CC
I
Power-down high impedance outputs
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Order Number
74ALVCF162835T
Package
Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500668
www.fairchildsemi.com
74ALVCF162835
Connection Diagram
Pin Descriptions
Pin Names
OE
LE
CLK
I
1
- I
18
O
1
- O
18
Description
Output Enable Input (Active LOW)
Latch Enable Input
Clock Input
Data Inputs
3-STATE Outputs
Truth Table
Inputs
OE
H
L
L
L
L
L
L
LE
X
H
H
L
L
L
L
CLK
X
X
X
I
n
X
L
H
L
H
X
X
Outputs
O
n
Z
L
H
L
H
O
0
(Note 1)
O
0
(Note 2)
↑
↑
H
L
H
=
Logic HIGH
L
=
Logic LOW
X
=
Don’t Care, but not floating
Z
=
High Impedance
↑ =
LOW-to-HIGH Clock Transition
Note 1:
Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 2:
Output level before the indicated steady-state input conditions
were established.
Logic Diagram
www.fairchildsemi.com
2
74ALVCF162835
Absolute Maximum Ratings
(Note 3)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 4)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to 4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 5)
Power Supply
Operating
Input Voltage
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 3:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 4:
I
O
Absolute Maximum Rating must be observed.
Note 5:
Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −2
mA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −8
mA
I
OH
= −12
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
2 mA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
8 mA
I
OL
=
12 mA
I
OH
High Level Output Current
1.65 - 3.6
1.65
2.3
2.3
3.0
2.7
3.0
1.65 - 3.6
1.65
2.3
2.3
3.0
2.7
3.0
1.65
2.3
2.7
3.0
I
OL
Low Level Output Current
1.65
2.3
2.7
3.0
I
I
I
OZ
I
OFF
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Power Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V, V
I
=
V
IH
or V
IL
0V
≤
(V
I
, V
O
)
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
1.65 - 3.6
1.65 - 3.6
0
3.6
2.7 - 3.6
V
CC
- 0.2
1.2
1.9
1.7
2.4
2
2
0.2
0.45
0.4
0.55
0.55
0.6
0.8
−2
−6
−8
−12
2
6
8
12
±5.0
±10
10
40
750
µA
µA
mA
µA
µA
mA
mA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
3
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