INTEGRATED CIRCUITS
74ALVC16834A
18-bit registered driver with
inverted register enable (3-State)
Product specification
Replaces datasheet 74ALVC16834 of 2000 Jan 04
IC24 Data Handbook
2000 Mar 14
Philips
Semiconductors
Philips Semiconductors
Product specification
18-bit registered driver with inverted register enable
(3-State)
74ALVC16834A
FEATURES
•
Wide supply voltage range of 1.2 V to 3.6 V
•
Complies with JEDEC standard no. 8-1A.
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Current drive
±
24 mA at 3.0 V
•
MULTIBYTE
TM
flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
PIN CONFIGURATION
NC
NC
Y
1
GND
Y
2
Y
3
V
CC
Y
4
Y
5
Y
6
GND
Y
7
Y
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
CP
GND
•
Output drive capability 50
Ω
transmission lines @ 85°C
•
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC16834A is an 18-bit registered driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Y
9
Y
10
Y
11
Y
12
GND
Y
13
Y
14
Y
15
V
CC
Y
16
Y
17
GND
Y
18
OE
LE
SH00194
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
Maximum clock frequency
Input capacitance
Input/Output capacitance
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
CONDITIONS
TYPICAL
2.3
2.6
2.5
350
4.0
8.0
13
3
pF
22
15
UNIT
t
PHL
/t
PLH
f
max
C
I
C
I/O
V
CC
= 3.3 V, C
L
= 50 pF
V
CC
= 3.3 V, C
L
= 50 pF
ns
MHz
pF
pF
C
PD
Power dissipation capacitance per buffer
V
I
= GND to V
CC1
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2000 Mar 14
2
853–2192 23314
Philips Semiconductors
Product specification
18-bit registered driver with inverted register enable
(3-State)
74ALVC16834A
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40°C to +85°C
ORDER CODE
74ALVC16834A DGG
DRAWING
NUMBER
SOT364-1
PIN DESCRIPTION
PIN NUMBER
1, 2, 55
3, 5, 6, 8, 9, 10, 12, 13,
14, 15, 16, 17, 19, 20,
21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46,
53, 56
7, 22, 35, 50
27
28
30
54, 52, 51, 49, 48, 47,
45, 44, 43, 42, 41, 40,
38, 37, 36, 34, 33, 31
SYMBOL
NC
Y
1
to Y
18
NAME AND FUNCTION
No connection
Data outputs
LOGIC SYMBOL
OE
GND
V
CC
OE
LE
CP
A
1
to A
18
Ground (0 V)
CP
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active LOW)
Clock input
Data inputs
A
1
D
LE
CP
Y
1
LE
TO THE 17 OTHER CHANNELS
SH00202
TYPICAL INPUT (DATA OR CONTROL)
V
CC
A1
SH00200
2000 Mar 14
3
Philips Semiconductors
Product specification
18-bit registered driver with inverted register enable
(3-State)
74ALVC16834A
LOGIC SYMBOL (IEEE/IEC)
OE
CP
LE
27
30
28
C3
G2
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
Y
13
Y
14
Y
15
Y
16
Y
17
Y
18
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1
∇
1
3D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
EN1
2C3
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
L
L
H
L
X
Z
↑
=
=
=
=
=
LE
X
L
L
H
H
H
H
CP
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
Z
L
H
L
H
Y
01
Y
02
OUTPUTS
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
SH00196
2000 Mar 14
4
Philips Semiconductors
Product specification
18-bit registered driver with inverted register enable
(3-State)
74ALVC16834A
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage 2.5 V range (for max. speed
performance @ 30 pF output load)
V
CC
DC supply voltage 3.3 V range (for max. speed
performance @ 50 pF output load)
DC supply voltage (for low-voltage applications)
V
I
V
O
T
amb
t
r
, t
f
DC Input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 2.3 to 3.0 V
V
CC
= 3.0 to 3.6 V
CONDITIONS
MIN
2.3
3.0
1.2
0
0
–40
0
0
MAX
2.7
3.6
3.6
V
CC
V
CC
+85
20
10
V
V
°C
ns/V
V
UNIT
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 8 mW/K
V
I
t0
For control pins
1
For data inputs
1
V
O
uV
CC
or V
O
t
0
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +4.6
–0.5 to V
CC
+0.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
600
UNIT
V
mA
V
mA
V
mA
mA
°C
mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2000 Mar 14
5
FPGA/CPLD
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