74ALVC163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
November 2001
Revised November 2001
74ALVC163245
Low Voltage 16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs
General Description
The ALVC163245 is a dual supply, 16-bit translating trans-
ceiver that is designed for 2 way asynchronous communi-
cation between busses at different supply voltages by
providing true signal translation. The supply rails consist of
V
CCA
, which is a higher potential rail operating at 2.3V to
3.6V and V
CCB
, which is the lower potential rail operating at
1.65V to 2.7V. (V
CCB
must be less than or equal to V
CCA
for proper device operation). This dual supply design
allows for translation from 1.8V to 2.5V busses to busses at
a higher potential, up to 3.3V.
The Transmit/Receive (T/R) input determines the direction
of data flow. Transmit (active-HIGH) enables data from
A Ports to B Ports; Receive (active-LOW) enables data
from B Ports to A Ports. The Output Enable (OE) input,
when HIGH, disables both A and B Ports by placing them
in a High-Z condition. The A Port interfaces with the higher
voltage bus (2.7V to 3.3V); The B Port interfaces with the
lower voltage bus (1.8V to 2.5V). Also the ALVC163245 is
designed so that the control pins (T/R
n
, OE
n
) are supplied
by V
CCB
.
The 74ALVC163245 is suitable for mixed voltage applica-
tions such as notebook computers using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
Features
s
Bidirectional interface between busses ranging from
1.65V to 3.6V
s
Supports Live Insertion and Withdrawal (Note 1)
s
Uses patented Quiet Series
noise/EMI reduction
circuitry
s
Functionally compatible with 74 series 16245
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human Body Model
>
2000V
Machine model
>
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1:
To ensure the high impedance state during power up or power
down, OE
n
should be tied to V
CCB
through a pull up resistor. The minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC163245GX
(Note 2)
74ALVC163245T
(Note 3)
Package Number
BGA54A
(Preliminary)
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2:
BGA package available in Tape and Reel only.
Note 3:
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
ds500695
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74ALVC163245
Logic Diagram
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names
OE
n
T/R
n
A
0
–A
15
B
0
–B
15
NC
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
B
0
B
2
B
4
B
6
B
8
B
10
B
12
B
14
B
15
2
NC
B
1
B
3
B
5
B
7
B
9
B
11
B
13
NC
3
T/R
1
NC
V
CCB
GND
GND
GND
V
CCB
NC
T/R
2
4
OE
1
NC
V
CCA
GND
GND
GND
V
CCA
NC
OE
2
5
NC
A
1
A
3
A
5
A
7
A
9
A
11
A
13
NC
6
A
0
A
2
A
4
A
6
A
8
A
10
A
12
A
14
A
15
Truth Tables
Inputs
Pin Assignment for FBGA
OE
1
L
L
H
Inputs
OE
2
L
L
H
T/R
2
L
H
X
Outputs
Bus B
8
–B
15
Data to Bus A
8
–A
15
Bus A
8
–A
15
Data to Bus B
8
–B
15
HIGH-Z State on A
8
–A
15
, B
8
–B
15
T/R
1
L
H
X
Outputs
Bus B
0
–B
7
Data to Bus A
0
–A
7
Bus A
0
–A
7
Data to Bus B
0
–B
7
HIGH Z State on A
0
–A
7
, B
0
–B
7
(Top Thru View)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs may not float)
Z
=
High Impedance
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2
74ALVC163245
74ALVC163245 Translator Power Up Sequence Recommendations
To guard against power up problems, some simple guide-
lines need to be adhered to. The 74ALVC163245 is
designed so that the control pins (T/R
n
, OE
n
) are supplied
by V
CCB
. Therefore the first recommendation is to begin by
powering up the control side of the device, V
CCB
. The OE
n
control pins should be ramped with or ahead of V
CCB
, this
will guard against bus contentions and oscillations as all
A Port and B Port outputs will be disabled. To ensure the
high impedance state during power up or power down, OE
n
should be tied to V
CCB
through a pull up resistor. The mini-
mum value of the resistor is determined by the current
sourcing capability of the driver. Second, the T/R
n
control
pins should be placed at logic LOW (0V) level, this will
ensure that the B-side bus pins are configured as inputs to
help guard against bus contention and oscillations. B-side
Data Inputs should be driven to a valid logic level (0V or
V
CCB
), this will prevent excessive current draw and oscilla-
tions. V
CCA
can then be powered up after V
CCB
, however
V
CCA
must be greater than or equal to V
CCB
to ensure
proper device operation. Upon completion of these steps
the device can then be configured for the users desired
operation. Following these steps will help to prevent possi-
ble damage to the translator device as well as other system
components.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74ALVC163245
Absolute Maximum Ratings
(Note 4)
Supply Voltage
V
CCA
V
CCB
DC Input Voltage (V
I
)
DC Output Voltage (V
I/O
) (Note 5)
A
n
B
n
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or Ground Current
Supply Pin (I
CC
or Ground)
Storage Temperature (T
STG
)
Recommended Operating
Conditions
(Note 6)
Power Supply (Note 7)
V
CCA
V
CCB
Input Voltage (V
I
) @ OE, T/R
Input/Output Voltage (V
I/O
)
A
n
B
n
Free Air Operating Temperature (T
A
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
0V to V
CCA
0V to V
CCB
2.3V to 3.6V
1.65V to 2.7V
0V to V
CCB
−
0.5V to
+
4.6V
−
0.5V to V
CCA
−
0.5V to
+
4.6V
−
0.5V to V
CCA
+
0.5V
−
0.5V to V
CCB
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
−
40
°
C to
+
85
°
C
10 ns/V
Note 4:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 5:
I
O
Absolute Maximum Rating must be observed.
Note 6:
Unused inputs or I/O pins must be held HIGH or LOW. They may
not float.
Note 7:
Operation requires: V
CCB
≤
V
CCA
DC Electrical Characteristics
Symbol
V
IHA
Parameter
HIGH Level Input Voltage A
n
Conditions
V
CCB
(V)
1.65 - 1.95
1.65 - 2.7
V
IHB
V
ILA
LOW Level Input Voltage
B
n
, T/R, OE
A
n
1.65 - 1.95
2.3 - 2.7
1.65 - 1.95
1.65 - 2.7
V
ILB
V
OHA
HIGH Level Output Voltage
B
n
, T/R, OE
I
OH
= −100 µA
I
OH
= −12
mA
I
OH
= −24
mA
V
OHB
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −4
mA
I
OH
= −12
mA
V
OLA
Low Level Output Voltage
I
OL
=
100
µA
I
OL
=
12 mA
I
OL
=
24 mA
V
OLB
Low Level Output Voltage
I
OL
=
100
µA
I
OL
=
4 mA
I
OL
=
12 mA
I
I
I
OZ
Input Leakage Current @ OE, T/R
3-STATE Output Leakage
0V
≤
V
I
≤
3.6V
0V
≤
V
O
≤
3.6V
OE
=
V
CCB
V
I
=
V
IH
or V
IL
I
OFF
I
CCA
/I
CCB
∆I
CC
Power Off Leakage Current
Quiescent Supply Current,
per supply, V
CCA
/ V
CCB
Increase in I
CC
per Input, B
n
, T/R, OE
Increase in I
CC
per Input, A
n
0≤ (V
I
, V
O
)
≤
3.6V
A
n
=
V
CCA
or GND
B
n
, OE, & T/R
=
V
CCB
or GND
V
I
=
V
CCB
– 0.6V
V
I
=
V
CCA
– 0.6V
0
1.65 - 2.7
1.65 - 2.2
1.65 - 2.2
0
2.3 - 3.6
2.3 - 3.6
2.3 - 3.6
10
40
750
750
µA
µA
µA
µA
1.65 - 2.7
2.3 - 3.6
±10
µA
1.65 - 1.95
2.3 - 2.7
1.65 - 2.7
1.65
1.65 - 2.3
1.65 - 2.7
1.65 - 1.95
2.3 - 2.7
1.65 - 2.7
1.65
1.65 - 2.3
1.65 - 2.7
1.65 - 1.95
2.3 -2.7
1.65 - 2.7
V
CCA
(V)
2.3 - 2.7
3.0 - 3.6
2.3 - 3.6
3.0 - 3.6
2.3 - 2.7
3.0 - 3.6
2.3 - 3.6
3.0 - 3.6
2.3 - 3.6
2.3 - 2.7
3.0 - 3.6
2.3 - 3.6
2.3 - 3.0
3.0
2.3 - 3.6
2.3 - 2.7
3.0 - 3.6
2.3 - 3.6
2.3 - 3.0
3.0
2.3 - 3.6
V
CCA
–0.2
1.7
2
V
CCB
–0.2
1.2
1.7
0.2
0.7
0.55
0.2
0.45
0.7
±5.0
µA
V
V
V
V
Min
1.7
2.0
V
0.65 x V
CCB
1.6
0.7
0.8
V
0.35 x V
CCB
0.7
Max
Units
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4
74ALVC163245
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
V
CCA
=
3.3
±
0.3
V
CCB
=
2.5
±
0.2
V
CCA
=
3.3
±
0.3
V
CCB
=
1.8
±
0.15
V
CCA
=
2.7
V
CCB
=
1.8
±
0.15
V
CCA
=
2.5
±
0.2
V
CCB
=
1.8
±
0.15
t
PHL
, t
PLH
Propagation Delay
B to A
V
CCA
=
3.3
±
0.3
V
CCB
=
2.5
±
0.2
V
CCA
=
3.3
±
0.3
V
CCB
=
1.8
±
0.15
V
CCA
=
2.7
V
CCB
=
1.8
±
0.15
V
CCA
=
2.5
±
0.2
V
CCB
=
1.8
±
0.15
t
PZL
, t
PZH
Output Enable Time
OE to B
V
CCA
=
3.3
±
0.3
V
CCB
=
2.5
±
0.2
V
CCA
=
3.3
±
0.3
V
CCB
=
1.8
±
0.15
V
CCA
=
2.7
V
CCB
=
1.8
±
0.15
V
CCA
=
2.5
±
0.2
V
CCB
=
1.8
±
0.15
t
PZL
, t
PZH
Output Enable Time
OE to A
V
CCA
=
3.3
±
0.3
V
CCB
=
2.5
±
0.2
V
CCA
=
3.3
±
0.3
V
CCB
=
1.8
±
0.15
V
CCA
=
2.7
V
CCB
=
1.8
±
0.15
V
CCA
=
2.5
±
0.2
V
CCB
=
1.8
±
0.15
t
PLZ
, t
PHZ
Output Disable Time
OE to B
V
CCA
=
3.3
±
0.3
V
CCB
=
2.5
±
0.2
V
CCA
=
3.3
±
0.3
V
CCB
=
1.8
±
0.15
V
CCA
=
2.7
V
CCB
=
1.8
±
0.15
V
CCA
=
2.5
±
0.2
V
CCB
=
1.8
±
0.15
t
PLZ
, t
PHZ
Output Disable Time
OE to A
V
CCA
=
3.3
±
0.3
V
CCB
=
2.5
±
0.2
V
CCA
=
3.3
±
0.3
V
CCB
=
1.8
±
0.15
V
CCA
=
2.7
V
CCB
=
1.8
±
0.18
V
CCA
=
2.5
±
0.2
V
CCB
=
1.8
±
0.18
1.1
1.1
1.3
5.3
6.1
5.7
0.8
5.2
0.6
5.6
ns
1.3
1.3
1.3
4.9
5.0
5.1
0.8
4.6
0.8
4.5
ns
1.1
1.1
1.3
4.5
5.6
5.8
0.8
5.3
0.6
5.1
ns
1.3
2.0
2.0
5.1
8.7
8.8
1.5
8.3
1.5
8.2
ns
1.1
1.1
1.3
4.5
5.6
6.0
0.8
5.5
0.6
5.1
ns
C
L
=
50 pF
Min
t
PHL
, t
PLH
Propagation Delay
A to B
1.3
2.0
2.0
Max
4.9
6.7
6.3
1.5
5.8
1.5
6.2
ns
C
L
=
30 pF
Min
Max
Units
5
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