INTEGRATED CIRCUITS
74ALS74A
Dual D-type flip-flop with set and reset
Product specification
IC05 Data Handbook
1996 Jul 01
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset
74ALS74A
DESCRIPTION
The 74ALS74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active-Low inputs and operate independently of the clock input.
When set and reset are inactive (High), data at the D input is
transferred to the Q and Q outputs on the Low-to-High transition of
the clock. Data must be stable just one setup time prior to the
Low-to-High transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
TYPICAL
SUPPLY CURRENT
(TOTAL)
3.0mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS74AN
74ALS74AD
74ALS74ADB
DRAWING
NUMBER
SOT27-1
SOT108-1
SOT337-1
14-pin plastic DIP
14-pin plastic SO
14-pin plastic SSOP
Type II
PIN CONFIGURATION
RD0
D0
CP0
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
RD1
D1
CP1
SD1
Q1
Q1
TYPE
74ALS74A
TYPICAL f
MAX
150MHz
SD0
Q0
Q0
GND
SF00045
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0, D1
CP0, CP1
SD0, SD1
RD0, RD1
Q0, Q1, Q0, Q1
Data inputs
Clock inputs (active rising edge)
Set inputs (active-Low)
Reset inputs (active-Low)
Data outputs
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
1.0/2.0
1.0/2.0
2.0/4.0
2.0/4.0
20/80
LOAD VALUE
HIGH/LOW
20µA/0.2mA
20µA/0.2mA
40µA/0.4mA
40µA/0.4mA
0.4mA/8mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
2
12
IEC/IEEE SYMBOL
4
D0 D1
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
Q0 Q0 Q1 Q1
11
12
13
V
CC
= Pin 14
GND = Pin 7
5
6
9
8
10
3
S
C1
&
5
2
1
1D
R
6
S
C2
2D
R
9
8
SF00046
SF00047
1996 Jul 01
2
853–1278 01670
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset
74ALS74A
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
OUTPUTS
D
X
X
X
h
l
X
Q
H
L
H
H
L
NC
Q
L
H
H
L
H
NC
OPERATING
MODE
Asynchronous set
Asynchronous reset
Undetermined*
Load “1”
Load “0”
Hold
SD
L
RD
H
L
L
H
H
H
CP
X
X
X
↑
↑
↑
SD
4, 10
RD
1, 13
5, 9
Q
H
L
H
CP
3, 11
6, 8
Q
H
H
D
2, 12
V
CC
= Pin 14
GND = Pin 7
SF00048
H = High voltage level
h = High state must be present one setup time prior to
Low-to-High clock transition
L = Low voltage level
l = Low state must be present one setup time prior to
Low-to-High clock transition
NC= No change from the previous setup
X = Don’t care
↑
= Low-to-High clock transition
↑
= Not Low-to-High clock transition
* = Both outputs will be High while both SD and RD are Low,
but the output states are unpredictable if SD and RD go
High simultaneously
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
16
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–0.4
8
+70
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
UNIT
1996 Jul 01
3
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset
74ALS74A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
OH
V
O
OL
V
IK
I
I
PARAMETER
High-level output voltage
TEST CONDITIONS
1
MIN
V
CC
=
±10%,
V
IL
= MAX, V
IH
= MIN
V
CC
= MIN, V
IL
= MAX,
,
,
V
IH
= MIN
V
CC
= MIN, I
I
= I
IK
Dn, CPn
SDn, RDn
Dn, CPn
I
IH
High–level
High level input current
SDn, RDn
Dn, CPn
I
IL
I
O
I
CC
Low level input current
Low–level
SDn, RDn
Output current
3
Supply current (total)
4
V
CC
= MAX, V
I
= 0 4V
MAX
0.4V
V
CC
= MAX, V
O
= 2.25V
V
CC
= MAX
–30
3.0
V
CC
= MAX, V
I
= 2 7V
MAX
2.7V
V
CC
= MAX, V
I
= 7 0V
MAX
7.0V
I
OH
= MAX
I
OL
= 4mA
I
OL
= 8mA
V
CC
– 2
0.25
0.35
–0.73
0.40
0.50
–1.5
0.1
0.2
20
40
–0.2
–0.4
–112
4.0
LIMITS
TYP
2
UNIT
MAX
V
V
V
V
mA
mA
µA
µA
mA
mA
mA
mA
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input
voltage
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, I
OS
.
4. Measure I
CC
with the Dn, CPn, and SDn grounded, then with Dn, CPn, and RDn grounded.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
f
max
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn or RD to Qn or Qn
Waveform 1
Waveform 1
Waveform 2, 3
80
3.0
3.0
1.0
3.0
14.0
14.0
8.0
10.0
MAX
MHz
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
rec
Setup time, High or Low
Dn to CPn
Hold time, High or Low
Dn to CPn
CPn Pulse width
High or Low
SDn or RDn Pulse width, Low
Recovery time, SDn or RDn to CPn
Waveform 1
Waveform 1
Waveform 1
Waveform 2, 3
Waveform 2, 3
6.0
6.0
0.0
0.0
6.0
6.0
6.0
6.0
MAX
ns
ns
ns
ns
ns
UNIT
1996 Jul 01
4
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset
74ALS74A
AC WAVEFORMS
For all waveforms, V
M
= 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn
V
M
t
su
(L)
V
M
t
h
(L)
1/f
max
V
M
t
su
(H)
V
M
t
h
(H)
CPn
V
M
t
w
(H)
t
PLH
V
M
t
w
(L)
V
M
t
PHL
Qn
V
M
t
PHL
V
M
t
PLH
Qn
V
M
V
M
SF00049
Waveform 1. Propagation Delay for Data to Output,
Data Setup and Hold Times, Clock Width,
and Maximum Clock Frequency
Dn
Dn
SDn
V
M
t
w
(L)
V
M
t
REC
RDn
V
M
t
w
(L)
V
M
t
REC
CPn
V
M
CPn
V
M
t
PLH
Qn
t
PHL
Qn
V
M
Qn
V
M
Qn
t
PLH
V
M
t
PHL
V
M
SC00040
SC00041
Waveform 2. Propagation Delay for Set to Output,
Set Pulse Width and Recovery Time for Set to Clock
Waveform 3. Propagation Delay for Reset to Output,
Reset Pulse Width and Recovery Time for Reset to Clock
1996 Jul 01
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
