INTEGRATED CIRCUITS
74ALS646/74ALS646–1
74ALS648/74ALS648–1
Transceiver/register
Product specification
IC05 Data Handbook
1991 Feb 08
Philips
Semiconductors
Philips Semiconductors
Product specification
Transceiver/register
74ALS646/646-1
74ALS648/648-1
FEATURES
74ALS646/74ALS646-1
74ALS648/74ALS648-1
Octal transceiver/register, non-inverting (3-State)
Octal transceiver/register, inverting (3-State)
TYPE
74ALS646/646-1
74ALS648/648-1
TYPICAL f
MAX
140MHz
140MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
48mA
54mA
•
Combines
one chip
74ALS245 and two 74ALS374 type functions in
•
Independent registers for A and B buses
•
Multiplexed real-time and stored data
•
Choice of non-inverting and inverting data paths
•
3-State outputs
•
The -1 version sink 48mA I
OL
within the
±5%
V
CC
range
DESCRIPTION
The 74ALS646/74ALS646-1 and 74ALS648/74ALS648-1
transceivers/registers consist of bus transceiver circuits with 3-State
outputs, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or the
internal registers. Data on the A or B bus will be clocked into the
registers as the appropriate clock pin goes High. Output enable
(OE) and direction (DIR) and select (SAB, SBA) pins are provided
for bus management.
The 74ALS646-1 and 74ALS648-1 will sink 48mA if the V
CC
is
limited to 5.0V
±0.25V.
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS646N, 74ALS646-1N,
74ALS648N, 74ALS648-1N
74ALS646D, 74ALS646-1D,
74ALS648D, 74ALS648-1D
DRAWING
NUMBER
24-pin plastic DIP
24-pin plastic SOL
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
A0 – A7
B0 – B7
CPAB
CPBA
SAB
SBA
DIR
OE
A0 – A7, B0 – B7
A0 – A7, B0 – B7
A inputs
B inputs
A-to-B clock input
B-to-A clock input
A-to-B select input
B-to-A select input
Data flow directional control input
Output enable input
Data outputs
Data outputs (-1 version)
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
750/240
750/480
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
15mA/24mA
15mA/48mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1991 Feb 08
2
853–1408 01670
Philips Semiconductors
Product specification
Transceiver/register
74ALS646/74ALS646-1
74ALS648/74ALS648-1
PIN CONFIGURATION – 74ALS646/646-1
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24 V
CC
23 CPBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
PIN CONFIGURATION – 74ALS648/648-1
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24 V
CC
23 CPBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
A6 10
A7 11
GND 12
A6 10
A7 11
GND 12
SC00118
SC00119
LOGIC SYMBOL – 74ALS646/646-1
4
5
6
7
8
9
10
11
LOGIC SYMBOL – 74ALS648/648-1
4
5
6
7
8
9
10
11
A0 A1 A2 A3 A4 A5 A6 A7
1
2
3
23
22
21
CPAB
SAB
DIR
SPBA
SBA
OE
B0 B1 B2 B3 B4 B5 B6 B7
1
2
3
23
22
21
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
SAB
DIR
SPBA
SBA
OE
B0 B1 B2 B3 B4 B5 B6 B7
V
CC
= Pin 24
GND = Pin 12
20
19
18
17
16
15
14
13
SC00120
V
CC
= Pin 24
GND = Pin 12
20
19
18
17
16
15
14
13
SC00121
IEC/IEEE SYMBOL – 74ALS646/646-1
21
3
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
1
6D
5
6
7
8
9
10
11
1
7
7
5
5
1
1
2
19
18
17
16
15
14
13
4D
20
IEC/IEEE SYMBOL – 74ALS648/648-1
21
3
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
1
1
6D
5
6
7
8
9
10
11
1
7
7
5
5
1
1
2
19
18
17
16
15
14
13
4D
20
23
22
1
2
23
22
1
2
4
4
SC00122
SC00123
1991 Feb 08
3
Philips Semiconductors
Product specification
Transceiver/register
74ALS646/74ALS646-1
74ALS648/74ALS648-1
BUS MANAGEMENT FUNCTIONS
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ALS646/646-1 and 74ALS648/648-1.
The select pins determine whether data is stored or transferred
through the device in real time.
The DIR determines which bus will receive data when the OE pin is
Low.
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
OE DIR CPAB CPBA SAB SBA
L
L
X
X
X
L
OE DIR CPAB CPBA SAB SBA
L
H
X
X
L
X
OE DIR CPAB CPBA SAB SBA
X
X
↑
X
X
X
X
X
X
↑
X
X
H
X
↑
↑
X
X
OE DIR CPAB CPBA SAB SBA
L
L
X H or L X
H
L
H H or L X
H
X
SF00392
1991 Feb 08
4
Philips Semiconductors
Product specification
Transceiver/register
74ALS646/74ALS646-1
74ALS648/74ALS648-1
LOGIC SYMBOL – 74ALS646/646-1
OE
DIR
21
3
LOGIC SYMBOL – 74ALS648/648-1
OE
DIR
21
3
23
CPBA
22
SBA
1
CPAB
2
SAB
23
CPBA
22
SBA
1
CPAB
2
SAB
1 OF 8 CHANNELS
1D
C1
1 OF 8 CHANNELS
1D
C1
A0
4
1D
C1
20
B0
A0
4
1D
C1
20
B0
V
CC
= Pin 24
GND = Pin 12
TO 7 OTHER CHANNELS
SC00124
V
CC
= Pin 24
GND = Pin 12
TO 7 OTHER CHANNELS
SC00125
FUNCTION TABLE
INPUTS
OE
X
X
H
H
L
L
L
L
DIR
X
X
X
X
L
L
H
H
CPAB
↑
X
↑
H or L
X
X
X
H or L
CPBA
X
↑
↑
H or L
X
H or L
X
X
SAB
X
X
X
X
X
X
L
H
SBA
X
X
X
X
L
H
X
X
An
Input
Unspecified*
Input
Input
Output
Output
Input
Input
DATA I/O
Bn
Unspecified*
Input
Input
Input
Input
Input
Output
Output
OPERATING MODE
74ALS646/74ALS646-1
Store A, B unspecified*
Store B, A unspecified*
Store A and B data
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
74ALS648/74ALS648-1
Store A, B unspecified*
Store B, A unspecified*
Store A and B data
Isolation, hold storage
Real time B data to A bus
Stored B data to A bus
Real time A data to B bus
Stored A data to B bus
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
* = The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
↑
= Low-to-High clock transition
1991 Feb 08
5
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