Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A
74ALS564A
FEATURES
74ALS373
74ALS563A/74ALS564A
Octal transparent latch, inverting (3-State)
Octal D flip-flop, inverting (3-State)
DESCRIPTION
The 74ALS563A is an octal transparent latch coupled to eight
3-State output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The 74ALS563A is a complementary version of the 74ALS373 and
has a broadside pinout configuration to facilitate PC board layout
and allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the inverted data that is present
one setup time before the High-to-Low enable transition.
The 74ALS564A is a complementary version of the 74ALS373 and
has a broadside pinout configuration to facilitate PC board layout
and allow easy interface with microprocessors.
It is an 8-bit edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
DRAWING
NUMBER
•
74ALS563A is broadside pinout and inverting version of
•
74ALS564A is broadside pinout and inverting version of
74ALS374
•
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•
Useful as an input or output port for microprocessors
•
3-State outputs for bus interfacing
•
Common output enable
•
74ALS573A and 74ALS574A are non-inverting version of
74ALS563B and 74ALS564A respectively
TYPICAL
SUPPLY CURRENT
(TOTAL)
12mA
15mA
TYPE
74ALS563A
74ALS564A
TYPICAL
PROPAGATION DELAY
6.0ns
6.0ns
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS563AN, 74ALS564AN
74ALS563AD, 74ALS564AD
20-pin plastic DIP
20-pin plastic SOL
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 – D7
E (74ALS563A)
OE
CP (74ALS564A)
Q0 – Q7
Data inputs
Enable input
Output enable input (active-Low)
Clock pulse input (active rising edge)
Data outputs
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
1.0/2.0
1.0/1.0
1.0/1.0
1.0/2.0
130/240
LOAD VALUE
HIGH/LOW
20µA/0.2mA
20µA/0.1mA
20µA/0.1mA
20µA/0.2mA
2.6mA/24mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
1996 Jul 01
2
853–1306 01670
Philips Semiconductors
Product specification
Latch/flip-flop
74ALS563A/74ALS564A
LOGIC DIAGRAM – 74ALS564A
D0
2
D
CP Q
CP
11
D1
3
D
CP Q
D2
4
D
CP Q
D3
5
D
CP Q
D4
6
D
CP Q
D5
7
D
CP Q
D6
8
D
CP Q
D7
9
D
CP Q
OE
V
CC
= Pin 20
GND = Pin 10
1
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SC00117
FUNCTION TABLE – 74ALS564A
INPUTS
OE
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
CP
↑
↑
↑
↑
↑
Dn
l
h
X
X
Dn
OUTPUTS
REGISTER
L
H
NC
NC
Dn
INTERNAL
Q0 – Q7
H
L
NC
Z
Z
Disable outputs
Load and read register
Hold
OPERATING MODE
High voltage level
High state must be present one setup time before the Low-to-High clock transition
Low voltage level
Low state must be present one setup time before the Low-to-High clock transition
No change
Don’t care
High impedance “off ” state
Low-to-High clock transition
Not Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
48
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
1996 Jul 01
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
