INTEGRATED CIRCUITS
74ALS175
Quad D flip–flop
Product specification
IC05 Data Handbook
1991 Feb 08
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad D flip-flop
74ALS175
FEATURES
•
Four edge-triggered D flip-flops
•
Buffered common clock
•
Buffered asynchronous master reset
•
True and complementary outputs
DESCRIPTION
The 74ALS175 is a quad, edge-triggered D-type flip-flops with
individual D inputs and both Q and Q outputs. The common buffered
clock (CP) and master reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of clock or data inputs
by a Low voltage level on the MR input. The device is useful for
applications where both true and complement outputs are required,
and the clock and master reset are common to all storage elements.
TYPICAL
SUPPLY CURRENT
(TOTAL)
7mA
PIN CONFIGURATION
MR
1
16 V
CC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CP
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND
8
SF00718
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS175N
74ALS175D
DRAWING
NUMBER
TYPE
74ALS175
TYPICAL
f
MAX
70MHz
16-pin plastic DIP
16-pin plastic SO
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Data inputs
Clock Pulse input (active rising edge)
Master Reset input (active-Low)
True outputs
Complementary outputs
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
20/80
20/80
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
0.4mA/8mA
0.4mA/8mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
4
5
12 13
IEC/IEEE SYMBOL
1
9
R
C1
2
4
1D
3
7
5
6
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
12
10
11
15
13
14
D0 D1 D2 D3
9
1
CP
MR
2
V
CC
= Pin 16
GND = Pin 8
3
7
6
10 11 15 14
SF00719
SF00720
1991 Feb 08
2
853–1024 01670
Philips Semiconductors
Product specification
Quad D flip-flop
74ALS175
LOGIC DIAGRAM
D0
4
CP
9
D1
5
D2
12
D3
13
D
Q
D
Q
D
Q
D
Q
CP
RD
MR
V
CC
= Pin 16
GND = Pin 8
1
3
2
Q0 Q0
CP
RD
CP
RD
CP
Q
RD
6
Q1
7
Q1
11
Q2
Q2
10
Q3
14
15
Q3
SF00721
FUNCTION TABLE
INPUTS
MR
L
H
H
CP
X
↑
↑
D
X
h
I
Q
n
L
H
L
OUTPUTS
Q
n
H
L
H
OPERATING
MODE
Reset (clear)
Load “1”
Load “0”
NOTES:
H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
X = Don’t care
↑
= Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
16
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–0.4
8
+70
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
1991 Feb 08
3
Philips Semiconductors
Product specification
Quad D flip-flop
74ALS175
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
OH
V
O
OL
V
IK
I
I
I
IH
I
IL
I
O
I
CC
PARAMETER
High-level output voltage
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Output current
3
Supply current (total)
TEST CONDITIONS
1
V
CC
±10%,
V
IL
= MAX, V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
,
,
V
IH
= MIN
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
O
= 2.25V
V
CC
= MAX
–30
7
I
OL
= 4mA
I
OL
= 8mA
LIMITS
MIN
V
CC
– 2
0.25
0.35
–0.73
0.4
0.50
–1.5
100
20
–0.1
–112
14
TYP
2
MAX
UNIT
V
V
V
V
µA
µA
mA
mA
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
OS
.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Propagation delay
CP to Qn or CP to Qn
Propagation delay, MR to Qn
Propagation delay, MR to Qn
Waveform 1
Waveform 1
Waveform 2
Waveform 2
60
3.0
5.0
3.0
8.0
13.0
16.0
13.0
18.0
MAX
MHz
ns
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
REC
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
CP pulse width,
High or Low
MR pulse width, Low
Recovery time, MR to CP
Waveform 3
Waveform 3
Waveform 1
Waveform 2
Waveform 2
6.0
6.0
0.0
0.0
8.0
8.0
6.0
6.0
MAX
ns
ns
ns
ns
ns
UNIT
1991 Feb 08
4
Philips Semiconductors
Product specification
Quad D flip-flop
74ALS175
AC WAVEFORMS
For all waveforms, V
M
= 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
MR
CP
V
M
t
w
(H)
t
PHL
V
M
t
PLH
Q
n
V
M
t
w
(L)
t
PLH
CP
V
M
t
PHL
t
PHL
Q
n
t
PLH
V
M
V
M
V
M
t
w
(L)
t
REC
V
M
V
M
V
M
Q
n
V
M
SF00722
Q
n
V
M
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Width,
and Maximum Clock Frequency
SF00723
Waveform 2. Master Reset Pulse Width,
Master Reset to Output Delay,
and Master Reset to Clock Recovery Time
Dn
V
M
t
su
(H)
V
M
t
h
(H)
V
M
t
su
(L)
V
M
t
h
(L)
CP
V
M
V
M
SC00064
Waveform 3. Data Setup and Hold Times
TEST CIRCUIT AND WAVEFORMS
V
CC
NEGATIVE
PULSE
V
IN
PULSE
GENERATOR
R
T
D.U.T.
V
OUT
90%
V
M
10%
t
THL (
t
f
f
)
C
L
R
L
t
w
V
M
10%
t
TLH (
t
r
)
0.3V
90%
AMP (V)
t
TLH (
t
r
)
90%
t
THL (
t
f
)
AMP (V)
90%
V
M
t
w
10%
0.3V
Test Circuit for Totem-pole Outputs
POSITIVE
PULSE
10%
V
M
DEFINITIONS:
R
L
= Load resistor;
see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
Family
Amplitude V
M
74ALS
3.5V
1.3V
Rep.Rate
1MHz
t
w
500ns
t
TLH
2.0ns
t
THL
2.0ns
SC00005
1991 Feb 08
5
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