INTEGRATED CIRCUITS
74ALS164
8–bit serial–in parallel–out shift register
Product specification
IC05 Data Handbook
1991 Feb 08
Philips
Semiconductors
Philips Semiconductors
Product specification
8-bit serial-in parallel-out shift register
74ALS164
FEATURES
•
Gated serial data inputs
•
Typical shift frequency of 75MHz
•
Asynchronous master reset
•
Buffered clock and data inputs
•
Fully synchronous data transfer
DESCRIPTION
The 74ALS164 is an 8-bit edge-triggered shift register with serial
data entry and an output from each of the eight stages. Data is
entered serially through one of two inputs (Dsa, Dsb); either input
can be used as an active-high enable for data entry through the
other input. Both inputs must be connected together or an unused
input must be tied High.
Data shifts one place to the right on each Low-to-high transition of
the clock (CP) input, and enters into Q0 the logical AND of the two
data inputs (Dsa, Dsb) that existed one setup time before the rising
edge. A Low level on the Master reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all outputs
Low.
PIN CONFIGURATION
Dsa
Dsb
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
14 V
CC
13 Q7
12 Q6
11 Q5
10 Q4
9
8
MR
CP
SF00717
TYPE
74ALS164
TYPICAL
f
MAX
75MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
10mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS164N
74ALS164D
DRAWING
NUMBER
SOT27-1
SOT108-1
14-pin plastic DIP
14-pin plastic SO
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
Dsa, Dsb
CP
MR
Q0 – Q7
Data inputs
Clock Pulse input (active rising edge)
Master Reset input (active-Low)
Data outputs
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
20/80
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
0.4mA/8mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
SRG8
8
1
2
9
1
R
&
C1/→
8
9
CP
MR
Dsa
Dsb
2
1D
3
4
5
6
10
Q0 Q1 Q3 Q4 Q0 Q1 Q3 Q4
3
4
5
6 10 11
12 13
11
12
V
CC
= Pin 14
GND = Pin 7
13
SF00713
SF00714
1991 Feb 08
2
853–1510 01670
Philips Semiconductors
Product specification
8-bit serial-in parallel-out shift register
74ALS164
LOGIC DIAGRAM
Dsa
Dsb
1
2
D
Q
CP
RD
8
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
CP
MR 9
V
CC
= Pin 14
GND = Pin 7
3
Q0
Q1
4
Q2
5
Q3
6
10
Q4
11
Q5
12
Q6
13
Q7
SF00715
MODE SELECT FUNCTION TABLE
INPUTS
MR
L
H
H
H
H
CP
X
↑
↑
↑
↑
Dsa
X
l
l
h
h
Dsb
X
l
h
l
h
Q0
L
L
L
L
H
Q1
L
q0
q0
q0
q0
Q2
L
q1
q1
q1
q1
OUTPUTS
Q3
L
q2
q2
q2
q2
Q4
L
q3
q3
q3
q3
Q5
L
q4
q4
q4
q4
Q6
L
q5
q5
q5
q5
Q7
L
q6
q6
q6
q6
Shift
OPERATING MODE
Reset (Clear)
NOTES:
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
qn = Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition.
X = Don’t care
↑
= Low-to-High clock transition
APPLICATION
The 74ALS164 can be cascaded to form synchronous shift registers of longer length.
Here, two devices are combined to form a 16-bit shift register.
CLEAR
CLOCK
CP
DATA
ENABLE
Dsa
Dsb
Q0
Q1
MR
Dsa
CP
MR
74ALS164
H
Q2
Q3
Q4
Q5
Q6
Q7
Dsb
Q0
Q1
74ALS164
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
SC00063
1991 Feb 08
3
Philips Semiconductors
Product specification
8-bit serial-in parallel-out shift register
74ALS164
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
16
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–0.4
8
+70
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
OH
V
O
OL
V
IK
I
I
I
IH
I
IL
I
O
I
CC
PARAMETER
High-level output voltage
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Output current
3
Supply current (total)
TEST CONDITIONS
1
V
CC
±10%,
V
IL
= MAX, V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
,
,
V
IH
= MIN
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
O
= 2.25V
V
CC
= MAX
–30
10
I
OL
= 4mA
I
OL
= 8mA
LIMITS
MIN
V
CC
– 2
0.25
0.35
–0.73
0.4
0.50
–1.5
100
20
–0.1
–112
15
TYP
2
MAX
UNIT
V
V
V
V
µA
µA
mA
mA
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
OS
.
1991 Feb 08
4
Philips Semiconductors
Product specification
8-bit serial-in parallel-out shift register
74ALS164
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PHL
Maximum clock frequency
Propagation delay
CP to Qn
Propagation delay, MR to Qn
Waveform 1
Waveform 1
Waveform 2
50
5.0
6.0
8.0
13.0
15.0
18.0
MAX
MHz
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
REC
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
Clock pulse width,
High or Low
MR pulse width, Low
Recovery time, MR to CP
Waveform 3
Waveform 3
Waveform 1
Waveform 2
Waveform 2
6.0
5.0
0
0
10.0
7.0
6.0
6.0
MAX
ns
ns
ns
ns
ns
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
MR
CP
V
M
t
w
(H)
t
PHL
V
M
t
w
(L)
t
PLH
V
M
CP
t
PHL
V
M
V
M
t
w
(L)
t
REC
V
M
V
M
V
M
Qn
SF00294
Qn
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Width,
and Maximum Clock Frequency
V
M
SC00065
Waveform 2. Master Reset Pulse Width,
Master Reset to Output Delay,
and Master Reset to Clock Recovery Time
Dn
V
M
t
su
(H)
V
M
t
h
(H)
V
M
t
su
(L)
V
M
t
h
(L)
CP
V
M
V
M
SC00064
Waveform 3. Data Setup and Hold Times
1991 Feb 08
5
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