Standard Products
UT8ER1M32 32Megabit SRAM MCM
UT8ER2M32 64Megabit SRAM MCM
UT8ER4M32 128Megabit SRAM MCM
Preliminary
Data Sheet
December 16, 2009
FEATURES
20ns Read, 10ns Write maximum access times available
Functionally compatible with traditional 1M, 2M and 4M
x 32 SRAM devices
CMOS compatible input and output levels, three-state
bidirectional data bus
- I/O Voltages 2.3V to 3.6V, 1.7V to 2.0Vcore
Available densities:
- UT8ER1M32: 33, 554, 432 bits
- UT8ER2M32: 67, 108, 864 bits
- UT8ER4M32: 134, 217, 728 bits
Operational environment:
- Total-dose: 100 krad(Si)
- SEL Immune: 111MeV-cm
2
/mg
- SEU error rate = 6.0x10
-16
errors/bit-day assuming
geosynchronous orbit, Adam’s 90% worst environment,
and 6600ns default Scrub Rate Period (=97% SRAM
availability)
Packaging option:
- 132-lead ceramic quad flatpack
Standard Microelectronics Drawing:
- UT8ER1M32: 5962-10202
- UT8ER2M32: 5962-10203
- UT8ER4M32: 5962-10204
- QML Q, Q+ and V pending
INTRODUCTION
The UT8ER1M32, UT8ER2M32, and UT8ER4M32 are high
performance CMOS static RAM multichip modules (MCMs)
organized as two, four or eight individual 524,288 words x 32
bits respectively. Easy memory expansion is provided by active
LOW chip enables (En), an active LOW output enable (G), and
three-state drivers. This device has a power-down feature that
reduces power consumption by more than 90% when deselected.
Autonomous (master) and demanded (slave) scrubbing
continues while deselected.
Writing to the device is accomplished by driving one of the chip
enable (En) inputs LOW and the write enable (W) input LOW.
Data on the 32 I/O pins (DQ0 through DQ31) is then written into
the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by driving one of the
chip enables (En) and output enable (G) LOW while driving
write enable (W) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
Note:
Only on En pin may be active at any time.
The 32 input/output pins (DQ0 through DQ31) are placed in a
high impedance state when the device is deselected (En HIGH),
the outputs are disabled (G HIGH), or during a write operation
(En LOW, W LOW).
En
E1
A[18:0]
W
G
512Kx32
(Master or Slave)
Die 1
DQ[31:0]
19
512Kx32
(Slave)
Die 2, 4, or 8
32
MBE
BUSY/NC
SCRUB
Figure 1. Block Diagram
1
FPGA/CPLD
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