INTEGRATED CIRCUITS
DATA SHEET
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
Product specification
File under Integrated Circuits, IC06
1999 Sep 17
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
•
Inputs accepts voltages higher than
V
CC
•
For AHC only:
operates with CMOS input levels
•
For AHCT only:
operates with TTL input levels
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
DESCRIPTION
The 74AHC/AHCT86 are high-speed
Si-gate CMOS devices and are pin
compatible with Low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74AHC/AHCT86 provides the
2-input EXCLUSIVE-OR function.
74AHC86; 74AHCT86
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
O
C
PD
PARAMETER
propagation delay
nA, nB to nY
input capacitance
power dissipation
capacitance
CONDITIONS
AHC
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
3.4
3.0
4.0
10
AHCT
3.4
3.0
4.0
12
ns
pF
pF
pF
UNIT
output capacitance V
I
= V
CC
or GND
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLE
See note 1.
INPUT
nA
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
nB
L
H
L
H
OUTPUT
nY
L
H
H
L
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC86D
74AHC86PW
74AHCT86D
74AHCT86PW
PACKAGES
NORTH AMERICA
PINS
74AHC86D
74AHC86PW DH
74AHCT86D
74AHCT86PW DH
14
14
14
14
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT402-1
SOT108-1
SOT402-1
1999 Sep 17
2
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
PINNING
PIN
1, 4, 9 and 12
2, 5, 10 and 13
3, 6, 8 and 11
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
data inputs
data inputs
data outputs
ground (0 V)
DC supply voltage
74AHC86; 74AHCT86
DESCRIPTION
handbook, halfpage
handbook, halfpage
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
MNA455
1
2
4
5
9
10
12
13
14 VCC
13 4B
12 4A
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
2Y
6
86
11 4Y
10 3B
9
3A
3Y
8
4Y
11
8 3Y
MNA456
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1
2
=
1
3
4
5
=
1
6
handbook, halfpage
A
9
10
Y
=
1
8
B
MNA458
12
13
=
1
11
MNA457
Fig.3 IEC logic symbol.
Fig.4 Logic diagram (one gate).
1999 Sep 17
3
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
RECOMMENDED OPERATING CONDITIONS
74AHC
SYMBOL
V
CC
V
I
V
O
T
amb
PARAMETER
DC supply voltage
input voltage
output voltage
operating ambient
temperature
see DC and AC
characteristics per device
CONDITIONS
MIN.
2.0
0
0
−40
−40
−
−
TYP.
5.0
−
−
+25
+25
−
−
74AHC86; 74AHCT86
74AHCT
UNIT
MAX.
5.5
5.5
V
CC
+85
+125
100
20
MIN.
4.5
0
0
−40
−40
−
−
TYP.
5.0
−
−
+25
+25
−
−
MAX.
5.5
5.5
V
CC
+85
+125
−
20
V
V
V
°C
°C
ns/V
t
r
,t
f
(∆t/∆f) input rise and fall
V
CC
= 3.3
±0.3
V
times except for
V
CC
= 5
±0.5
V
Schmitt trigger inputs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO package: above 70
°C
the value of P
D
derates linearly with 8 mW/K.
For TSSOP package: above 60
°C
the value of P
D
derates linearly with 5.5 mW/K.
PARAMETER
DC supply voltage
input voltage
DC input diode current
DC output diode current
DC output source or sink current
DC V
CC
or GND current
storage temperature
power dissipation per package
for temperature range:
−40
to +125
°C;
note 2
V
I
<
−0.5
V; note 1
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V; note 1
−0.5
V < V
O
< V
CC
+ 0.5 V
CONDITIONS
MIN.
−0.5
−0.5
−
−
−
−
−65
−
MAX.
+7.0
+7.0
−20
±20
±25
±75
+150
500
UNIT
V
V
mA
mA
mA
mA
°C
mW
1999 Sep 17
4
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
DC CHARACTERISTICS
74AHC86; 74AHCT86
Family 74AHC
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
OTHER
V
IH
HIGH-level input
voltage
V
CC
(V)
2.0
3.0
5.5
V
IL
LOW-level input
voltage
2.0
3.0
5.5
V
OH
HIGH-level output
voltage; all
outputs
HIGH-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
=
−50 µA
V
I
= V
IH
or V
IL
;
I
O
=
−4.0
mA
V
I
= V
IH
or V
IL
;
I
O
=
−8.0
mA
V
OL
LOW-level output
voltage; all
outputs
LOW-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
= 50
µA
V
I
= V
IH
or V
IL
;
I
O
= 4.0 mA
V
I
= V
IH
or V
IL
;
I
O
= 8.0 mA
I
I
I
OZ
I
CC
C
I
input leakage
current
3-state output
OFF current
quiescent supply
current
input capacitance
V
I
= V
CC
or GND
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
5.5
MIN.
1.5
2.1
−
−
−
1.9
2.9
4.4
−
−
−
−
−
2.0
3.0
4.5
25
TYP.
−
−
−
0.5
0.9
1.65
−
−
−
−
−
0.1
0.1
0.1
0.36
0.36
0.1
T
amb
(°C)
−40
to +85
−
−
0.5
0.9
1.65
−
−
−
−40
to +125 UNIT
−
−
0.5
0.9
1.65
−
−
−
V
V
V
MAX. MIN. MAX. MIN. MAX.
1.5
2.1
−
−
−
1.9
2.9
4.4
1.5
2.1
−
−
−
1.9
2.9
4.4
V
3.85
−
3.85
−
3.85
−
2.58
−
3.94
−
−
−
−
−
−
−
−
−
−
0
0
0
−
−
−
−
−
3
2.48
−
3.8
−
−
−
−
−
−
−
0.1
0.1
0.1
0.44
0.44
1.0
±2.5
20
10
2.40
−
3.70
−
−
−
−
−
−
−
−
−
−
0.1
0.1
0.1
0.55
0.55
2.0
V
V
µA
V
I
= V
IH
or V
IL
;
5.5
V
O
= V
CC
or GND
V
I
= V
CC
or GND;
I
O
= 0
5.5
−
±0.25 −
2.0
10
−
−
±10.0 µA
40
10
µA
pF
1999 Sep 17
5
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