Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
•
Balanced propagation delays
•
All inputs have Schmitt-trigger actions
•
Inputs accept voltages higher than V
CC
•
For AHC only: operates with CMOS input levels
•
For AHCT only: operates with TTL input levels
•
Specified from
−40
to +85
°C
and from−40 to +125
°C.
APPLICATIONS
•
Serial-to-parallel data conversion
•
Remote control holding register.
DESCRIPTION
74AHC595; 74AHCT595
The 74AHC/AHCT595 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT595 is an 8-stage serial shift register
with a storage register and 3-state outputs. The shift
register has separate clocks.
Data is shifted on the positive-going transitions of the
SH
CP
input. The data in each register is transferred to the
storage register on a positive-going transition of the ST
CP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (D
S
) and a serial
standard output (Q
7
’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
SH
CP
to Q
7
’
ST
CP
to Q
n
MR to Q
7
’
C
I
f
max
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
3. All 9 outputs switching.
input capacitance
maximum clock frequency
power dissipation capacitance
CONDITIONS
AHC
C
L
= 15 pF; V
CC
= 5 V
4.0
4.2
4.4
3.0
170
C
L
= 50 pF; f = 1 MHz; notes 1, 2 and 3 180
3.8
4.0
4.6
3.0
170
190
ns
ns
ns
pF
MHz
pF
AHCT
UNIT
2000 Mar 15
2
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
FUNCTION TABLE
See note 1.
INPUT
SH
CP
X
X
X
↑
ST
CP
X
↑
X
X
OE
L
L
H
L
MR
L
L
L
H
D
S
X
X
X
H
OUTPUT
74AHC595; 74AHCT595
FUNCTION
Q
7
’
L
L
L
Q
6
’
Q
n
NC
L
Z
NC
a LOW level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear. Parallel outputs in high impedance
OFF-state.
logic HIGH level shifted into shift register stage 0.
Contents of all shift register stages shifted through, e.g.
previous state of stage 6 (internal Q
6
’) appears on the
serial output (Q
7
’).
contents of shift register stages (internal Q
n
’) are
transferred to the storage register and parallel output
stages
contents of shift register shifted through. Previous
contents of the shift register is transferred to the storage
register and the parallel output stages.
X
↑
L
H
X
NC
Q
n
’
↑
↑
L
H
X
Q
6
’
Q
n
’
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH transition;
↓
= HIGH-to-LOW transition;
X = don’t care;
NC = no change;
Z = high impedance OFF-state.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
74AHC595D
74AHC595PW
74AHCT595D
74AHCT595PW
TEMPERATURE
RANGE
−40
to +125
°C
PINS
16
16
16
16
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT109-1
SOT403-1
SOT109-1
SOT403-1
2000 Mar 15
3
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
PINNING
PIN
1, 2, 3, 4, 5, 6, 7 and 15
8
9
10
11
12
13
14
16
GND
Q
7
’
MR
SH
CP
ST
CP
OE
D
S
V
CC
SYMBOL
Q
1
, Q
2
, Q
3
, Q
4
, Q
5
, Q
6
, Q
7
and Q
0
74AHC595; 74AHCT595
DESCRIPTION
parallel data output
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
DC supply voltage
handbook, halfpage
handbook, halfpage
11
12
9
15
1
2
3
4
5
6
7
Q1 1
Q2 2
Q3 3
Q4 4
Q5 5
Q6 6
Q7 7
GND 8
MNA551
16 VCC
15 Q0
14 DS
13 OE
SHCP STCP
Q7'
Q0
Q1
14
Q2
DS
Q3
Q4
Q5
Q6
Q7
MR
10
OE
13
MNA552
595
12 STCP
11 SHCP
10 MR
9 Q7'
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2000 Mar 15
4
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