Philips Semiconductors
Product specification
Quad 2-input multiplexer
FEATURES
•
ESD protection: HBM EIA/JESD22-A114-A
exceeds 2000 V MM EIA/JESD22-A115-A
exceeds 200 V CDM EIA/JESD22-C101
exceeds 1000 V
•
Balanced propagation delays
•
All inputs have Schmitt-trigger actions
•
Multiple input enable for easy expansion
•
Ideal for memory chip select decoding
•
Inputs accept voltages higher than V
CC
•
For AHC only: operates with CMOS input levels
•
For AHCT only: operates with TTL input levels
•
Specified from
−40
to +85 and +125
°C.
FUNCTION TABLE
See note 1.
INPUT
E
H
L
L
L
L
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC157D
74AHC157PW
74AHCT157D
74AHCT157PW
PACKAGES
NORTH AMERICA
PINS
74AHC157D
74AHC157PW DH
74AHCT157D
74AHCT157PW DH
16
16
16
16
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
S
X
L
L
H
H
nI
0
X
L
H
X
X
nI
1
X
X
X
L
H
OUTPUT
nY
L
L
H
L
H
DESCRIPTION
74AHC157;
74AHCT157
The 74AHC/AHCT157 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT157 are quad 2-input multiplexers which
select 4 bits of data from two sources under the control of
a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs (1Y to 4Y)
are forced LOW regardless of all other input conditions.
Moving the data from two groups of registers to four
common output buses is a common use of the ‘157’. The
state of the common data select input (S) determines the
particular register from which the data comes. It can also
be used as a function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
The ‘157’ is the logic implementation of a 4-pole, 2-position
switch, where the position of the switch is determine by the
logic levels applied to S.
The logic equations are:
1Y = E
×
(1I
1
×
S + 1I
0
×
S);
2Y = E
×
(2I
1
×
S + 2I
0
×
S);
3Y = E
×
(3I
1
×
S + 3I
0
×
S);
4Y = E
×
(4I
1
×
S + 4I
0
×
S).
The ‘157’ is identical to the ‘158’ but has non-inverting
(true) outputs.
CODE
SOT109-1
SOT403-1
SOT109-1
SOT403-1
1999 Sep 24
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
nI
0
, nI
1
to nY
S to nY
E to nY
C
I
C
O
C
PD
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 50 pF; f = 1 MHz; notes 1 and 2
4 outputs switching via S
1 output switching via I
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
PINNING
PIN
1
2, 5, 11 and 14
3, 6, 10 and 13
4, 7, 9 and 12
8
15
16
S
1I
0
to 4I
0
1I
1
to 4I
1
1Y to 4Y
GND
E
V
CC
SYMBOL
31
13
41
16
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
3.2
4.5
3.7
3.0
4.0
3.4
5.1
4.0
3.0
4.0
CONDITIONS
AHC
74AHC157;
74AHCT157
UNIT
AHCT
ns
ns
ns
pF
pF
pF
pF
DESCRIPTION
common data select input
data inputs from source 0
data inputs from source 1
multiplexer outputs
ground (0 V)
enable input (active LOW)
DC supply voltage
1999 Sep 24
3
嵌入式系统
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