74ACTQ843 Quiet Series™ 9-Bit Transparent Latch with 3-STATE Outputs
March 1990
Revised December 1998
74ACTQ843
Quiet Series™ 9-Bit Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths. The
ACTQ843 utilizes Fairchild FACT Quiet Series™ technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO™ output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Inputs and outputs on opposite sides of package for
easy interface with microprocessors
s
Improved latch-up immunity
s
Outputs source/sink 24 mA
s
ACTQ843 has TTL-compatible inputs
s
Functionally and pin-compatible to AMD’s AM29843
s
3-STATE outputs for bus interfacing
Ordering Code:
Order Number
74ACTQ843SC
74ACTQ843SPC
Package Number
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for DIP and SOIC
Pin Descriptions
Pin Names
D
0
–D
8
O
0
–O
8
OE
LE
CLR
PRE
FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
Preset
© 1999 Fairchild Semiconductor Corporation
DS010689.prf
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74ACTQ843
Functional Description
The ACTQ843 consists of nine D-type latches with 3-
STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asyn-
chronous operation, as the output transition follows the
data in transition. On the LE HIGH-to-LOW transition, the
data that meets the setup times is latched. Data appears
on the bus when the Output Enable (OE) is LOW. When
OE is HIGH, the bus output is in the high impedance state.
In addition to the LE and OE pins, the ACTQ843 has a
Clear (CLR) pin and a Preset (PRE) pin. These pins are
ideal for parity bus interfacing in high performance sys-
tems. When CLR is LOW, the outputs are LOW if OE is
LOW. When CLR is HIGH, data can be entered into the
latch. When PRE is LOW, the outputs are HIGH if OE is
LOW. Preset overrides CLR.
Function Table
Inputs
CLR PRE
H
H
H
H
H
H
H
L
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
NC
=
No Change
Internal
LE
H
H
L
H
H
L
X
X
X
L
L
D
L
H
X
L
H
X
X
X
X
X
X
Q
L
H
NC
L
H
NC
H
L
H
L
H
Outputs
O
Z
Z
Z
L
H
NC
H
L
H
Z
Z
Function
OE
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
L
H
L
High Z
High Z
Latched
Transparent
Transparent
Latched
Preset
Clear
Preset
Clear/High Z
Preset/High Z
Logic Diagram
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2
74ACTQ843
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source
or Sink Current
±
300 mA
±50
mA
−65°C
to
+150°C
±50
mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Junction Temperature (T
J
)
PDIP
140°C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆V/∆t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT™ circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.0
1.2
0.8
V
(Note 4)(Note 6)
5.0
1.9
2.0
V
5.0
−0.6
−1.2
V
5.0
1.1
1.5
V
5.5
5.5
5.5
5.5
8.0
0.6
1.5
75
−75
80.0
mA
mA
mA
µA
5.5
±
0.5
±
5.0
µA
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
(Note 4)(Note 5)
(Note 4)(Note 6)
5.5
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±
0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
V
IN
=
V
IL
or V
IH
3.76
4.76
0.1
0.1
V
IN
=
V
IL
or V
IH
0.44
0.44
±
1.0
µA
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
V
I
OH
=
24 mA
I
OH
=
24 mA (Note 2)
I
OUT
=
50
µA
V
V
Units
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
3
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74ACTQ843
DC Electrical Characteristics
Note 4:
DIP package.
(Continued)
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6:
Max number of data inputs (n) switching. (n
−
1) inputs switching 0V to 3V. Input-under-test switching:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1 MHz.
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHL
t
PLH
t
OSLH
t
OSHL
Parameter
Propagation Delay
D
n
to O
n
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
n
Propagation Delay
PRE to O
n
Propagation Delay
CLR to O
n
Output Enable Time
OE to O
n
Output Enable Time
OE to O
n
Output Disable Time
OE to O
n
Output Disable Time
OE to O
n
Propagation Delay
PRE to O
n
Propagation Delay
CLR to O
n
Output to Output Skew (Note 8)
D
n
to O
n
5.0
0.5
1.5
1.5
ns
5.0
2.5
7.3
11.0
2.0
12.0
ns
5.0
2.5
6.7
10.0
2.0
11.0
ns
5.0
1.5
5.1
8.0
1.0
8.5
ns
5.0
1.5
5.0
8.0
1.0
8.5
ns
5.0
2.5
7.5
9.5
2.0
10.5
ns
5.0
2.5
7.2
9.5
2.0
10.5
ns
5.0
2.5
7.2
11.0
2.0
12.0
ns
5.0
2.5
7.3
10.0
2.0
11.0
ns
5.0
2.5
6.9
9.0
2.0
10.0
ns
5.0
2.5
7.1
9.0
2.0
10.0
ns
5.0
2.5
6.7
9.5
2.0
10.0
ns
(V)
(Note 7)
5.0
Min
2.5
T
A
= +25°C
C
L
=
50 pF
Typ
6.2
Max
9.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
2.0
Max
10.0
ns
Units
Note 7:
Voltage Range 5.0 is 5.0V
±0.5V.
Note 8:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
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4
74ACTQ843
AC Operating Requirements
V
CC
Symbol
Parameter
(V)
(Note 9)
t
S
Setup Time, HIGH or LOW
D
n
to LE
t
H
Hold Time, HIGH or LOW
D
n
to LE
t
W
t
W
t
W
t
rec
t
rec
LE Pulse Width, HIGH
PRE Pulse Width, LOW
CLR Pulse Width, LOW
PRE Recovery Time
CLR Recovery Time
5.0
5.0
5.0
5.0
5.0
4.0
4.0
4.0
2.0
2.0
4.0
4.0
4.0
2.0
2.0
ns
ns
ns
ns
ns
5.0
1.5
1.5
ns
5.0
T
A
= +25°C
C
L
=
50 pF
Typ
3.0
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
3.0
ns
Units
Note 9:
Voltage Range 5.0 is 5.0V
±0.5V.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
52
Units
pF
pF
V
CC
=
OPEN
V
CC
=
5.0V
Conditions
5
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