74ACTQ18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
September 1991
Revised November 1999
74ACTQ18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ18823 contains eighteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP), Clear (CLR), Clock Enable (EN) and
Output Enable (OE) are common to each byte and can be
shorted together for full 18-bit operation.
The ACTQ18823 utilizes Fairchild’s Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector for
superior performance.
Features
s
Utilizes Fairchild’s FACT Quiet Series technology
s
Broadside pinout allows for easy board layout
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number
74ACTQ18823SSC
74ACTQ18823MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
CLR
n
EN
n
CP
n
I
0
–I
17
O
0
–O
17
Description
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010953
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74ACTQ18823
Connection Diagram
Functional Description
The ACTQ18823 consists of eighteen D-type edge-trig-
gered flip-flops. These have 3-STATE outputs for bus sys-
tems organized with inputs and outputs on opposite sides.
The device is byte controlled with each byte functioning
identically, but independent of the other. The control pins
can be shorted together to obtain full 16-bit operation. The
following description applies to each byte. The buffered
clock (CP
n
) and buffered Output Enable (OE
n
) are com-
mon to all flip-flops within that byte. The flip-flops will store
the state of their individual D inputs that meet set-up and
hold time requirements on the LOW-to-HIGH CP
n
transi-
tion. With OE
n
LOW, the contents of the flip-flops are avail-
able at the outputs. When OE
n
is HIGH, the outputs go to
the impedance state. Operation of the OE
n
input does not
affect the state of the flip-flops. In addition to the Clock and
Output Enable pins, there are Clear (CLR
n
) and Clock
Enable (EN
n
) pins. These devices are ideal for parity bus
interfacing in high performance systems.
When CLR
n
is LOW and OE
n
is LOW, the outputs are
LOW. When CLR
n
is HIGH, data can be entered into the
flip-flops. When EN
n
is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the EN
n
is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Function Table
OE
H
H
H
L
H
L
H
H
L
L
CLR
X
X
L
L
H
H
H
H
H
H
(Note 1)
Inputs
EN
L
L
X
X
H
H
L
L
L
L
CP
Internal
Output
O
n
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
X
X
X
I
n
L
H
X
X
X
X
L
H
L
H
Q
L
H
L
L
NC
NC
L
H
L
H
H= HIGH Voltage Level
L= LOW Voltage Level
X= Immaterial
Z= High Impedance
=
LOW-to-HIGH Transition
NC= No Change
X
Note 1:
The table represents the logic for one byte. The two bytes are independent of each other and function identically.
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2
74ACTQ18823
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
3
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74ACTQ18823
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+0.5V
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin
Junction Temperature
PDIP/SOIC
Storage Temperature
ESD Last Passing Voltage (Min)
+140°C
−65°C
to
+150°C
4000V
±
50 mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
±
50 mA
−20
mA
+20
mA
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
Parameter
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
V
OLP
V
OLV
V
OHP
V
OHV
V
IHD
V
ILD
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Maximum Quiescent Supply Current
Minimum Dynamic
Output Current (Note 4)
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Maximum Overshoot
Minimum V
CC
Droop
Minimum High Voltage Level
Maximum Low Dynamic Input Voltage Level
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
5.0
5.0
0.5
−0.5
0.8
−0.8
0.6
8.0
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.5
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±5.0
±1.0
1.5
80.0
75
−75
µA
µA
mA
µA
mA
mA
V
V
V
V
V
V
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−0.1V
V
OUT
=
0.1V
or V
CC
−0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 3)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 3)
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
, GND
V
I
=
V
CC
−2.1V
V
IN
=
V
CC
or GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
(Note 6)(Note 7)
(Note 6)(Note 7)
(Note 5)(Note 7)
(Note 5)(Note 7)
(Note 5)(Note 8)
(Note 5)(Note 8)
V
OH
+
1.0 V
OH
+
1.5
V
OH
−
1.0 V
OH
−
1.8
1.7
1.2
2.0
1.2
Note 3:
All outputs loaded; thresholds associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
Worst case package.
Note 6:
Maximum number of outputs that can switch simultaneously is n. (n
−
1) outputs are switched LOW and one output held LOW.
Note 7:
Maximum number of outputs that can switch simultaneously is n. (n
−
1) outputs are switched HIGH and one output held HIGH.
Note 8:
Maximum number of data inputs (n) switching. (n
−
1) input switching 0V to 3V. Input under test switching 3V to threshold (V
ILD
).
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74ACTQ18823
AC Electrical Characteristics
V
CC
Symbol
f
MAX
t
PHL
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
Note 9:
Voltage Range 5.0 is 5.0V
±
0.5V.
T
A
= +25°C
C
L
=
50 pF
Min
100
2.0
2.0
9.0
9.0
9.0
9.0
9.0
7.0
8.0
Typ
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
90
2.0
2.0
2.0
2.0
2.0
1.5
1.5
9.5
9.5
9.5
10.0
10.0
7.5
8.5
Max
MHz
ns
ns
ns
ns
Units
Parameter
Maximum Clock
Frequency
Propagation Delay
CP
n
to O
n
Propagation Delay
CLR
n
to O
n
Output Enable Time
Output Disable Time
(V)
(Note 9)
5.0
5.0
5.0
5.0
5.0
2.0
2.0
2.0
1.5
1.5
AC Operating Requirements
V
CC
Symbol
t
S
t
H
t
S
t
H
Parameter
Setup Time, HIGH or LOW,
Input to Clock
Hold Time, HIGH or LOW,
Input to Clock
Setup Time, HIGH or LOW,
Enable to Clock
Hold Time, HIGH or LOW,
Enable to Clock
t
W
t
W
t
REC
CP
n
Pulse Width,
HIGH or LOW
CLR
n
Pulse Width,
HIGH or LOW
Recovery Time,
CLR
n
to CP
n
Note 10:
Voltage Range 5.0 is 5.0V
±
0.5V.
T
A
= +25°C
C
L
=
50 pF
Typ
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
Units
(V)
(Note 10)
5.0
5.0
5.0
5.0
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
ns
ns
ns
ns
5.0
4.0
4.0
ns
5.0
5.0
4.0
6.0
4.0
6.0
ns
ns
5
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