74ACT715•74ACT715-R Programmable Video Sync Generator
November 1988
Revised December 1998
74ACT715•74ACT715-R
Programmable Video Sync Generator
General Description
The ACT715 and ACT715-R are 20-pin TTL-input compati-
ble devices capable of generating Horizontal, Vertical and
Composite Sync and Blank signals for televisions and
monitors. All pulse widths are completely definable by the
user. The devices are capable of generating signals for
both interlaced and noninterlaced modes of operation.
Equalization and serration pulses can be introduced into
the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the sys-
tem architecture. Line rate and field/frame rate are all a
function of the values programmed into the data registers,
the status register, and the input clock frequency.
The ACT715 is mask programmed to default to a Clock
Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming
before operation.
The ACT715-R is the same as the ACT715 in all respects
except that the ACT715-R is mask programmed to default
to a Clock Enabled state. Bit 10 of the Status Register
defaults to a logic “1”. Although completely (re)programma-
ble, the ACT715-R version is better suited for applications
using the default 14.31818 MHz RS-170 register values.
This feature allows power-up directly into operation, follow-
ing a single CLEAR pulse.
Features
s
Maximum Input Clock Frequency
>
130 MHz
s
Interlaced and non-interlaced formats available
s
Separate or composite horizontal and vertical Sync and
Blank signals available
s
Complete control of pulse width via register
programming
s
All inputs are TTL compatible
s
8 mA drive on all outputs
s
Default RS170/NTSC values mask programmed into
registers
s
ACT715-R is mask programmed to default to a Clock
Enable state for easier start-up into 14.31818 MHz
RS170 timing
Ordering Code:
Order Number
74ACT715SC
74ACT715PC
74ACT715-RSC
74ACT715-RPC
Package Number
M20B
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for DIP and SOIC
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010137.prf
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74ACT715•74ACT715-R
Logic Block Diagram
Pin Description
There are a Total of 13 inputs and 5 outputs on the
ACT715.
Data Inputs D0–D7:
The Data Input pins connect to the
Address Register and the Data Input Register.
ADDR/DATA:
The ADDR/DATA signal is latched into the
device on the falling edge of the LOAD signal. The signal
determines if an address (0) or data (1) is present on the
data bus.
L/HBYTE:
The L/HBYTE signal is latched into the device
on the falling edge of the LOAD signal. The signal deter-
mines if data will be read into the 8 LSB’s (0) or the 4
MSB’s (1) of the Data Registers. A 1 on this pin when an
ADDR/DATA is a 0 enables Auto-Load Mode.
LOAD:
The LOAD control pin loads data into the Address
or Data Registers on the rising edge. ADDR/DATA and L/
HBYTE data is loaded into the device on the falling edge of
the LOAD. The LOAD pin has been implemented as a
Schmitt trigger input for better noise immunity.
CLOCK:
System CLOCK input from which all timing is
derived. The clock pin has been implemented as a Schmitt
trigger for better noise immunity. The CLOCK and the
LOAD signal are asynchronous and independent. Output
state changes occur on the falling edge of CLOCK.
CLR:
The CLEAR pin is an asynchronous input that initial-
izes the device when it is HIGH. Initialization consists of
setting all registers to their mask programmed values, and
initializing all counters, comparators and registers. The
CLEAR pin has been implemented as a Schmitt trigger for
better noise immunity. A CLEAR pulse should be asserted
by the user immediately after power-up to ensure proper
initialization of the registers—even if the user plans to
(re)program the device.
Note:
A CLEAR pulse will disable the CLOCK on the ACT715 and will
enable the CLOCK on the ACT715-R.
ODD/EVEN:
Output that identifies if display is in odd
(HIGH) or even (LOW) field of interlace when device is in
interlaced mode of operation. In noninterlaced mode of
operation this output is always HIGH. Data can be serially
scanned out on this pin during Scan Mode.
VCSYNC:
Outputs Vertical or Composite Sync signal
based on value of the Status Register. Equalization and
Serration pulses will (if enabled) be output on the VCSYNC
signal in composite mode only.
VCBLANK:
Outputs Vertical or Composite Blanking signal
based on value of the Status Register.
HBLHDR:
Outputs Horizontal Blanking signal, Horizontal
Gating signal or Cursor Position based on value of the Sta-
tus Register.
HSYNVDR:
Outputs Horizontal Sync signal, Vertical Gat-
ing signal or Vertical Interrupt signal based on value of Sta-
tus Register.
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2
74ACT715•74ACT715-R
Register Description
All of the data registers are 12 bits wide. Width’s of all
pulses are defined by specifying the start count and end
count of all pulses. Horizontal pulses are specified with-
respect-to the number of clock pulses per line and vertical
pulses are specified with-respect-to the number of lines per
frame.
REG0—STATUS REGISTER
The Status Register controls the mode of operation, the
signals that are output and the polarity of these outputs.
The default value for the Status Register is 0 (000 Hex) for
the ACT715 and is “1024” (400 Hex) for the ACT715-R.
Bits 0–2
B
2
B
1
B
0
VCBLANK VCSYNC HBLHDR HSYNVDR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CSYNC
CSYNC
VSYNC
VSYNC
CSYNC
CSYNC
VSYNC
VSYNC
Bits 3–4
B
4
0
B
3
0
Equalization
(DEFAULT)
0
1
1
1
0
1
Non Interlaced Double Serration
Illegal State
Mode of Operation
Interlaced Double Serration and
HGATE
HBLANK
HGATE
HBLANK
CUSOR
HBLANK
CUSOR
HBLANK
VGATE
VGATE
HSYNC
HSYNC
VINT
VINT
HSYNC
HSYNC
(DEFAULT)
B10—
Disable System Clock (0)
Enable System Clock (1)
Default values for B10 are “0” in the ACT715
and “1” in the ACT715-R.
B11—
Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for
internal testing only.
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizon-
tal Sync and Blank pulses.
REG1—
REG2—
REG3—
REG4—
Horizontal Front Porch
Horizontal Sync Pulse End Time
Horizontal Blanking Width
Horizontal Interval Width # of Clocks
per Line
VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of
lines per frame, and the characteristics of the Vertical Blank
and Sync Pulses.
REG5—
REG6—
REG7—
REG8—
Vertical Front Porch
Vertical Sync Pulse End Time
Vertical Blanking Width
Vertical Interval Width
per Frame
# of Lines
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
These registers determine the width of equalization and
serration pulses and the vertical interval over which they
occur.
REG 9—
Equalization Pulse Width End Time
Non Interlaced Single Serration and Equalization REG10— Serration Pulse Width End Time
Double Equalization and Serration mode will output equal-
REG11— Equalization/Serration Pulse Vertical
ization and serration pulses at twice the HSYNC frequency
Interval Start Time
(i.e., 2 equalization or serration pulses for every HSYNC
REG12— Equalization/Serration Pulse Vertical
pulse). Single Equalization and Serration mode will output
Interval End Time
an equalization or serration pulse for every HSYNC pulse.
In Interlaced mode equalization and serration pulses will be
VERTICAL INTERRUPT SPECIFICATION REGISTERS
output during the VBLANK period of every odd and even
These Registers determine the width of the Vertical Inter-
field. Interlaced Single Equalization and Serration mode is
rupt signal if used.
not possible with this part.
REG13—
Bits 5–8
Bits 5 through 8 control the polarity of the outputs. A value
of zero in these bit locations indicates an output pulse
active LOW. A value of 1 indicates an active HIGH pulse.
B5—
B6—
B7—
B8—
Bits 9–11
Bits 9 through 11 enable several different features of the
device.
B9—
Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
VCBLANK Polarity
VCSYNC Polarity
HBLHDR Polarity
HSYNVDR Polarity
REG14—
Vertical Interrupt Activate Time
Vertical Interrupt Deactivate Time
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating sig-
nals.
REG15—
REG16—
REG17—
REG18—
Horizontal Cursor Position Start Time
Horizontal Cursor Position End Time
Vertical Cursor Position Start Time
Vertical Cursor Position End Time
3
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74ACT715•74ACT715-R
Signal Specification
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not 0. All values of the horizontal timing registers
are referenced to the falling edge of the Horizontal Blank
signal (see Figure 1). Since the first CLOCK edge, CLOCK
#1, causes the first falling edge of the Horizontal Blank ref-
erence pulse, edges referenced to this first Horizontal edge
are n
+
1 CLOCKs away, where “n” is the width of the tim-
ing in question. Registers 1, 2, and 3 are programmed in
this manner. The horizontal counters start at 1 and count
until HMAX. The value of HMAX must be divisible by 2.
This limitation is imposed because during interlace opera-
tion this value is internally divided by 2 in order to generate
serration and equalization pulses at 2
×
the horizontal fre-
quency. Horizontal signals will change on the falling edge
of the CLOCK signal. Signal specifications are shown
below.
FIGURE 1. Horizontal Waveform Specification
Horizontal Period (HPER)
Horizontal Blanking Width:
Horizontal Sync Width:
Horizontal Front Porch:
=
REG(4)
×
ckper
=
[REG(3)
−
1]
×
ckper
Vertical Syncing Width
=
[REG(6)
−
REG(5)]
×
hper/n
Vertical Front Porch
=
[REG(5)
−
1]
×
hper/n
where
n
=
1 for noninterlaced
n
=
2 for interlaced
COMPOSITE SYNC AND BLANK SPECIFICATION
Composite Sync and Blank signals are created by logically
ANDing (ORing) the active LOW (HIGH) signals of the cor-
responding vertical and horizontal components of these
signals. The Composite Sync signal may also include ser-
ration and/or equalization pulses. The Serration pulse inter-
val occurs in place of the Vertical Sync interval.
Equalization pulses occur preceding and/or following the
Serration pulses. The width and location of these pulses
can be programmed through the registers shown below.
(See Figure 3.)
Horizontal Equalization PW
=
[REG(9)
−
REG(1)]
×
ckper
REG 9
=
(HFP)
+
(HEQP)
+
1
Horizontal Serration PW:
=
[REG(4)/n
REG(10)]
×
ckper
Where
+
REG(1)
−
=
[REG(2)
−
REG(1)]
×
ckper
=
[REG(1)
−
1]
×
ckper
VERTICAL SYNC AND BLANK SPECIFICATION
All vertical signals are defined in terms of number of lines
per frame. This is true in both interlaced and noninterlaced
modes of operation. Care must be taken to not specify the
Vertical Registers in terms of lines per field. Since the first
CLOCK edge, CLOCK #1, causes the first falling edge of
the Vertical Blank (first Horizontal Blank) reference pulse,
edges referenced to this first edge are n
+
1 lines away,
where “n” is the width of the timing in question. Registers 5,
6, and 7 are programmed in this manner. Also, in the inter-
laced mode, vertical timing is based on half-lines. There-
fore registers 5, 6, and 7 must contain a value twice the
total horizontal (odd and even) plus 1 (as described
above). In non-interlaced mode, all vertical timing is based
on whole-lines. Register 8 is always based on whole-lines
and does not add 1 for the first clock. The vertical counter
starts at the value of 1 and counts until the value of VMAX.
No restrictions exist on the values placed in the vertical
registers. Vertical Blank will change on the leading edge of
HBLANK. Vertical Sync will change on the leading edge of
HSYNC. (See Figure 2.) Vertical Frame Period (VPER)
=
REG(8)
×
hper
Vertical Field Period (VPER/n)
=
REG(8)
×
hper/n
Vertical Blanking Width
=
[REG(7)
−
1]
×
hper/n
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4
REG 10
=
(HFP)
+
(HPER/2)
−
(HSERR)
+
1
n
=
1 for noninterlaced single serration/equal-
ization
n
=
2 for noninterlaced double serration/equal-
ization
n
=
2 for interlaced operation
74ACT715•74ACT715-R
FIGURE 2. Vertical Waveform Specification
FIGURE 3. Equalization/Serration Interval Programming
HORIZONTAL AND VERTICAL GATING SIGNALS
Horizontal Drive and Vertical Drive outputs can be utilized
as general purpose Gating Signals. Horizontal and Vertical
Gating Signals are available for use when Composite Sync
and Blank signals are selected and the value of Bit 2 of the
Status Register is 0. The Vertical Gating signal will change
in the same manner as that specified for the Vertical Blank.
Horizontal Gating Signal Width
=
[REG(16)
−
REG(15)]
×
ckper
Vertical Gating Signal Width:
hper
=
[REG(18)
−
REG(17)]
×
CURSOR POSITION AND VERTICAL INTERRUPT
The Cursor Position and Vertical Interrupt signal are avail-
able when Composite Sync and Blank signals are selected
and Bit 2 of the Status Register is set to the value of 1. The
Cursor Position generates a single pulse of n clocks wide
during every line that the cursor is specified. The signals
are generated by logically ORing (ANDing) the active LOW
(HIGH) signals specified by the registers used for generat-
ing Horizontal and Vertical Gating signals. The Vertical
Interrupt signal generates a pulse during the vertical inter-
val specified. The Vertical Interrupt signal will change in the
same manner as that specified for the Vertical Blanking sig-
nal.
Horizontal Cursor Width
=
[REG(16)
−
REG(15)]
×
ckper
Vertical Cursor Width
=
[REG(18)
−
REG(17)]
×
hper
Vertical Interrupt Width
=
[REG(14)
−
REG(13)]
×
hper
5
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