74AC377 • 74ACT377 Octal D-Type Flip-Flop with Clock Enable
November 1988
Revised March 2005
74AC377 • 74ACT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
s
I
CC
reduced by 50%
s
Ideal for addressable register applications
s
Clock enable for address and data synchronization
applications
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Outputs source/sink 24 mA
s
See 273 for master reset version
s
See 373 for transparent latch version
s
See 374 for 3-STATE version
s
ACT377 has TTL-compatible inputs
Ordering Code:
Order Number
74AC377SC
74AC377SJ
74AC377MTC
74AC377MTCX_NL
(Note 1)
74AC377PC
74ACT377SC
74ACT377SJ
74ACT377MTC
74ACT377PC
Package
Number
M20B
M20D
MTC20
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
CE
Q
0
–Q
7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009961
www.fairchildsemi.com
74AC377 • 74ACT377
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
140
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
AC
ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (
'
V/
'
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
0.5V
V
CC
0.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
0.5V
V
CC
0.5V
40
q
C to
85
q
C
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
125 mV/ns
DC Electrical Characteristics for AC
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 5)
I
OLD
I
OHD
I
CC
(Note 5)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
4.0
0.002
0.001
0.001
T
A
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
Guaranteed Limits
Units
V
OUT
V
Conditions
0.1V
or V
CC
0.1V
V
OUT
0.1V
V
or V
CC
0.1V
V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
V
I
OH
I
OH
I
OH
I
OUT
V
IN
12 mA
24 mA
24 mA (Note 3)
50
P
A
V
IL
or V
IH
12 mA
24 mA
24 mA (Note 3)
V
CC
,
1.65V Max
3.85V Min
V
CC
or GND
0.44
0.44
0.44
V
I
OL
I
OL
I
OL
V
I
r
0.1
r
1.0
75
P
A
mA
mA
GND
V
OLD
V
OHD
V
IN
75
40.0
P
A
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3
www.fairchildsemi.com
74AC377 • 74ACT377
AC Operating Requirements for AC
V
CC
Symbol
Parameter
(V)
(Note 9)
t
S
t
H
t
S
t
H
t
W
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
Setup Time, HIGH or LOW
CE to CP
Hold Time, HIGH or LOW
CE to CP
CP Pulse Width
HIGH or LOW
Note 9:
Voltage Range 3.3 is 3.0V
r
0.3V
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
Typ
3.5
2.5
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
Guaranteed Minimum
5.5
4.0
0
1.0
6.0
4.0
0
1.0
5.5
4.0
6.0
4.5
0
1.0
7.5
4.5
0
1.0
6.0
4.5
ns
ns
ns
ns
ns
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
2.0
1.0
4.0
2.5
3.5
2.0
3.5
2.5
AC Electrical Characteristics for ACT
V
CC
Symbol
Parameter
(V)
(Note 10)
f
MAX
t
PLH
t
PHL
Maximum Clock Frequency
Propagation Delay
CP to Q
n
Propagation Delay
CP to Q
n
Note 10:
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
Min
140
3.0
3.5
25
q
C
50 pF
Typ
175
6.5
7.0
9.0
10.0
Max
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
MHz
10.0
11.0
ns
ns
Units
Min
125
2.5
2.5
5.0
5.0
5.0
AC Operating Requirements for ACT
V
CC
Symbol
Parameter
(V)
(Note 11)
t
S
t
H
t
S
t
H
t
W
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
Setup Time, HIGH or LOW
CE to CP
Hold Time, HIGH or LOW
CE to CP
CP Pulse Width
HIGH or LOW
Note 11:
Voltage Range 5.0 is 5.0V
r
0.5V
T
A
C
L
Typ
2.5
25
q
C
50 pF
T
A
40
q
C to
85
q
C
C
L
50 pF
Units
Guaranteed Minimum
4.5
1.0
4.5
1.0
4.0
5.5
1.0
5.5
1.0
4.5
ns
ns
ns
ns
ns
5.0
5.0
5.0
5.0
5.0
1.0
2.5
1.0
2.0
Capacitance
Symbol
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
Parameter
Typ
4.5
90.0
Units
pF
pF
V
CC
V
CC
OPEN
5.0V
Conditions
5
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