74ACT18825 18-Bit Buffer/Line Driver with 3-STATE Outputs
August 1999
Revised October 1999
74ACT18825
18-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACT18825 contains eighteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 18-bit operation.
Features
s
Broadside pinout allows for easy board layout
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT18825SSC
74ACT18825MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
I
0
–I
17
O
0
–O
17
Description
Output Enable Input (Active LOW)
Inputs
Outputs
FACT™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS0500292
www.fairchildsemi.com
74ACT18825
Functional Description
The ACT18825 contains eighteen non-inverting buffers
with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but indepen-
dently of the other. The control pins may be shorted
together to obtain full 8-bit operation. The 3-STATE outputs
are controlled by an Output Enable (OE
n
) input for each
byte. When OE
n
is LOW, the outputs are in 2-state mode.
When OE
n
is HIGH, the outputs are in the high impedance
mode, but this does not interfere with entering new data
into the inputs.
Truth Table
Inputs
Byte 1 (0:8) Byte 2 (8:17)
OE
1
L
H
X
L
L
H
L
OE
2
L
X
H
L
L
H
L
OE
3
L
L
L
H
X
H
L
OE
4
L
L
L
X
H
H
L
I
0
–I
8
I
9
–I
17
O
0
–O
8
O
9
–O
17
H
X
X
L
H
X
L
H
L
H
X
X
X
L
H
Z
Z
L
H
Z
L
H
L
H
Z
Z
Z
L
Outputs
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
Logic Diagram
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2
74ACT18825
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+0.5V
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin
Storage Temperature
±50
mA
−65°C
to
+150°C
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
±50
mA
−20
mA
+20
mA
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT™ circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZ
I
IN
I
CCT
I
CC
I
OLD
I
OHD
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum I
CC
/Input
Maximum Quiescent Supply Current
Minimum Dynamic
Output Current (Note 3)
5.5
5.5
5.5
5.5
5.5
0.6
8.0
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.5
±
0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±5.0
±
1.0
1.5
80.0
75
−75
µA
µA
mA
µA
mA
mA
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−0.1V
V
OUT
=
0.1V
or V
CC
−0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
, GND
V
I
=
V
CC
−2.1V
V
IN
=
V
CC
or GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
3
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74ACT18825
AC Electrical Characteristics
V
CC
Symbol
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
Parameter
Propagation Delay
Data to Output
Output Enable
Time
Output Disable
Time
(V)
(Note 4)
5.0
5.0
5.0
Min
2.0
2.0
2.0
2.0
1.5
1.5
T
A
= +25°C
C
L
=
50 pF
Typ
5.3
5.6
6.3
6.5
4.5
5.1
Max
8.4
8.7
9.6
9.7
7.3
8.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
2.0
2.0
2.0
2.0
1.5
1.5
Max
9.0
9.2
10.3
10.4
7.6
8.8
ns
ns
ns
Units
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ
4.5
95
Units
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
Conditions
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4
74ACT18825
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
5
www.fairchildsemi.com
stm32/stm8
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