74ACT16543 16-Bit Registered Transceiver with 3-STATE Outputs
August 1999
Revised October 1999
74ACT16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACT16543 contains sixteen non-inverting transceivers
containing two sets of D-type registers for temporary stor-
age of data flowing in either direction. Each byte has sepa-
rate control inputs which can be shorted together for full
16-bit operation. Separate Latch Enable and Output
Enable inputs are provided for each register to permit inde-
pendent input and output control in either direction of data
flow.
Features
s
Independent registers for A and B buses
s
Separate controls for data flow in each direction
s
Back-to-back registers for storage
Multiplexed real-time and stored data transfers
s
Separate control logic for each byte
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT16543SSC
74ACT16543MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEAB
n
OEBA
n
CEAB
n
CEBA
n
LEAB
n
LEBA
n
A
0
–A
15
B
0
–B
15
Descriptions
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS500301
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74ACT16543
Functional Description
The ACT16543 contains sixteen non-inverting transceivers
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. The control pins may be shorted together to obtain
full 16-bit operation. The following description applies to
each byte. For data flow from A to B, for example, the A-to-
B Enable (CEAB
n
) input must be LOW in order to enter
data from A
0
–A
15
or take data from B
0
–B
15
, as indicated in
the Data I/O Control Table. With CEAB
n
LOW, a LOW sig-
nal on the A-to-B Latch Enable (LEAB
n
) input makes the A-
to-B latches transparent; a subsequent LOW-to-HIGH tran-
sition of the LEAB
n
signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB
n
and OEAB
n
both LOW, the 3-STATE B output
buffers are active and reflect the data present at the output
of the A latches. Control of data flow from B to A is similar,
but using the CEBA
n
, LEBA
n
and OEBA
n
inputs.
Data I/O Control Table
Inputs
CEAB
n
H
X
L
X
L
LEAB
n
X
H
L
X
X
OEAB
n
X
X
X
H
L
Latch Status
(Byte n)
Latched
Latched
Transparent
—
—
Output
Buffers
(Byte n)
High Z
—
—
High Z
Driving
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
A-to-B data flow shown; B-to-A flow control
is the same, except using CEBA
n
, LEBA
n
and OEBA
n
Logic Diagrams
Byte 1
(0:7)
Byte 2
(8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACT16543
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin
Storage Temperature
±50
mA
−65°C
to
+150°C
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
±50
mA
−20
mA
+20
mA
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT™ circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZT
I
IN
I
CCT
I
CC
I
OLD
I
OHD
Maximum I/O
Leakage Current
Maximum Input
Leakage Current
Maximum I
CC
/Input
Max Quiescent
Supply Current
Minimum Dynamic
Output Current (Note 3)
5.5
5.5
5.5
5.5
5.5
0.6
8.0
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.5
±0.1
T
A
= −40°C
to+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±5.0
±1.0
1.5
80.0
75
−75
µA
µA
mA
µA
mA
mA
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
=
−24
mA
I
OH
=
−24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
= 24 mA
I
OL
= 24 mA (Note 2)
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
,
GND
V
I
=
V
CC
−
2.1V
V
IN
=
V
CC
or GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms; one output loaded at a time.
3
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74ACT16543
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
Parameter
Propagation Delay
Transparent Mode
A
n
to B
n
or B
n
to A
n
Propagation Delay
LEBA
n
, LEAB
n
to A
n
, B
n
Output Enable Time
OEBA
n
or OEAB
n
to A
n
or B
n
CEBA
n
or CEAB
n
to A
n
or B
n
t
PHZ
t
PLZ
Output Disable Time
OEBA
n
or OEAB
n
to A
n
or B
n
CEBA
n
or CEAB
n
to A
n
or B
n
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V.
T
A
= +25°C
C
L
=
50 pF
Min
3.8
3.5
4.7
Typ
5.9
5.5
6.9
6.3
6.3
7.3
Max
8.3
7.9
9.8
9.0
9.2
10.3
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
3.0
2.6
3.4
3.1
3.0
3.6
Max
9.0
8.5
10.8
9.8
9.9
10.3
ns
ns
ns
Units
(V)
(Note 4)
5.0
5.0
3.9
4.2
5.0
4.9
2.8
5.0
2.6
5.2
5.0
8.0
7.6
2.1
2.0
8.3
8.1
ns
AC Operating Requirements
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW
A
n
or B
n
to LEBA
n
or LEAB
n
Hold Time, HIGH or LOW
A
n
or B
n
to LEBA
n
or LEAB
n
Latch Enable, B to A
Pulse Width, LOW
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Units
(V)
(Note 5)
5.0
Guaranteed Minimum
3.0
3.0
ns
5.0
5.0
1.5
4.0
1.5
4.0
ns
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation.Capacitance
Typ
4.5
95.0
Units
pF
pF
V
CC
=
5.0V
V
CC
=
5.0V
Conditions
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4
74ACT16543
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (SSOP), JEDEC MO-153, 6.1mm Wide
Package Number MS56A
5
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