Operational environment; total dose irradiation testing to MIL-
STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1Mrad(Si)
- Latchup immune (LET > 100 MeV-cm
2
/mg)
Packaging options:
- 16-lead flatpack (0.7 grams)
Standard Microcircuit Drawing 5962-98651
- QML Q and V compliant part
Compatible with ANSI/TIA/EIA-644 Standard
INTRODUCTION
The UT54LVDS031LV Quad Driver is a quad CMOS differential
line driver designed for applications requiring ultra low power
dissipation and high data rates. The device is designed to support
data rates in excess of 400.0 Mbps (200 MHz) utilizing Low
Voltage Differential Signaling (LVDS) technology.
The UT54LVDS031LV accepts low voltage TTL input levels and
translates them to low voltage (340mV) differential output signals.
In addition, the driver supports a three-state function that may be
used to disable the output stage, disabling the load current, and thus
dropping the device to an ultra low idle power state.
The UT54LVDS031LV and companion quad line receiver
UT54LVDS032LV provide new alternatives to high power pseudo-
ECL devices for high speed point-to-point interface applications.
All pins have Cold Spare buffers. These buffers will be high
impedance when V
DD
is tied to V
SS
.
D
IN1
D
OUT1+
D1
D
OUT1-
D
IN2
D
OUT2+
D2
D
OUT2-
D
OUT3+
D3
D
OUT3-
D
OUT4+
D4
D
OUT4-
D
IN3
D
IN4
EN
EN
Figure 1. UT54LVDS031LV Quad Driver Block Diagram
36-00-06-004
Version 1.0.1
1
Cobham Semiconductor Solutions
www.aeroflex.com/LVDS
APPLICATIONS INFORMATION
The UT54LVDS031LV driver’s intended use is primarily in an
uncomplicated point-to-point configuration as is shown in Figure
3. This configuration provides a clean signaling environment for
quick edge rates of the drivers. The receiver is connected to the
driver through a balanced media such as a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the
characteristic impedance of the media is in the range of 100. A
termination resistor of 100should be selected to match the media
and is located as close to the receiver input pins as possible. The
termination resistor converts the current sourced by the driver into
voltages that are detected by the receiver. Other configurations are
possible such as a multi-receiver configuration, but the effects of
a mid-stream connector(s), cable stub(s), and other impedance
discontinuities, as well as ground shifting, noise margin limits, and
total termination loading must be taken into account.
D
IN1
D
OUT1+
D
OUT1-
EN
D
OUT2-
D
OUT2+
D
IN2
V
SS
1
2
3
4
5
6
7
8
UT54LVDS031LV
Driver
16
15
14
13
12
11
10
9
V
DD
D
IN4
D
OUT4+
D
OUT4-
EN
D
OUT3-
D
OUT3+
D
IN3
Figure 2. UT54LVDS031LV Pinout
ENABLE
TRUTH TABLE
Enables
EN
L
EN
H
Input
D
IN
X
L
H
Z
L
H
Output
D
OUT+
D
OUT-
Z
H
L
DATA
INPUT
1/4 UT54LVDS031LV
RT 100
1/4 UT54LVDS032LV
+
-
DATA
OUTPUT
Figure 3. Point-to-Point Application
All other combinations
of ENABLE inputs
PIN DESCRIPTION
Pin No.
1, 7, 9, 15
2, 6, 10, 14
3, 5, 11, 13
4
12
16
8
Name
D
IN
D
OUT+
D
OUT-
EN
EN
V
DD
V
SS
Description
Driver input pin, TTL/CMOS
compatible
Non-inverting driver output pin,
LVDS levels
Inverting driver output pin,
LVDS levels
Active high enable pin, OR-ed
with EN
Active low enable pin, OR-ed
with EN
Power supply pin, +3.3V + 0.3V
Ground pin
The UT54LVDS031LV differential line driver is a balanced current
source design. A current mode driver, has a high output impedance
and supplies a constant current for a range of loads (a voltage mode
driver on the other hand supplies a constant voltage for a range of
loads). Current is switched through the load in one direction to
produce a logic state and in the other direction to produce the other
logic state. The current mode
requires
(as discussed above) that a
resistive termination be employed to terminate the signal and to
complete the loop as shown in Figure 3. AC or unterminated
configurations are not allowed. The 3.4mA loop current will
develop a differential voltage of 340mV across the 100
termination resistor which the receiver detects with a 240mV
minimum differential noise margin neglecting resistive line losses
(driven signal minus receiver threshold (340mV - 100mV =
240mV)). The signal is centered around +1.2V (Driver Offset,
V
OS
) with respect to ground as shown in Figure 4.
Note:
The
steady-state voltage (V
SS
) peak-to-peak swing is twice the
differential voltage (V
OD
) and is typically 680mV.
36-00-06-004
Version 1.0.1
2
Cobham Semiconductor Solutions
www.aeroflex.com/LVDS
3V
D
IN
D
OUT-
SINGLE-ENDED
D
OUT+
V
0D
0V
V
OH
V
OS
V
OL
+V
OD
0V (DIFF.)
0V
-V
OD
D
OUT+
- D
OUT-
DIFFERENTIAL OUTPUT
Note: The footprint of the UT54LVDS031LV is the same as the
industry standard Quad Differential (RS-422) Driver.
V
SS
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quiescent
current remains relatively flat versus switching frequency.
Whereas the RS-422 voltage mode driver increases
exponentially in most cases between 20 MHz - 50 MHz. This
is due to the overlap current that flows between the rails of the
device when the internal gates switch. Whereas the current
mode driver switches a fixed current between its output without
any substantial overlap current. This is similar to some ECL
and PECL devices, but without the heavy static I
CC
requirements of the ECL/PECL design. LVDS requires 80%
less current than similar PECL devices. AC specifications for
the driver are a tenfold improvement over other existing RS-
422 drivers.
The Three-State function allows the driver outputs to be
disabled, thus obtaining an even lower power state when the
transmission of data is not required.
Figure 4. Driver Output Levels
3
OPERATIONAL ENVIRONMENT
PARAMETER
Total Ionizing Dose (TID)
Single Event Latchup (SEL)
Neutron Fluence
1
Notes:1.
Guarnteed but not tested.
LIMIT
1.0E6
>100
1.0E13
UNITS
rad(Si)
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
PARAMETER
DC supply voltage
Voltage on any pin during operation
Voltage on any pin during cold spare
T
STG
P
D
T
J
JC
I
I
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 4.0V
-0.3 to (V
DD
+ 0.3V)
-.3 to 4.0V
-65 to +150C
1.25 W
+150C
10C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
3.0 to 3.6V
-55 to +125C
0V to V
DD
36-00-06-004
Version 1.0.1
4
Cobham Semiconductor Solutions
www.aeroflex.com/LVDS
DC ELECTRICAL CHARACTERISTICS*
1, 2
(V
DD
= 3.3V + 0.3V; -55C < T
C
< +125C); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
V
IH
V
IL
V
OL
V
OH
I
IN
I
CS
V
OD1
V
OD1
V
OS
V
OS
V
CL3
I
OS2, 3
I
OZ3
I
CCL3
I
CCZ3
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input leakage current
Cold Spare Leakage Current
Differential Output Voltage
Change in Magnitude of V
OD
for
Complementary Output States
Offset Voltage
(TTL)
(TTL)
R
L
= 100
R
L
= 100
V
IN
= V
DD
or GND, V
DD
= 3.6V
V
IN
=3.6V, V
DD
=V
SS
R
L
= 100
(figure 5)
R
L
= 100
(figure 5)
Voh + Vol
-
R
L
= 100,
Vos = --------------------------
2
CONDITION
MIN
2.0
V
SS
0.925
MAX
V
DD
0.8
UNIT
V
V
V
1.650
-10
-20
250
+10
+20
400
35
1.125
1.450
V
A
mV
mV
V
Change in Magnitude of V
OS
for
Complementary Output States
Input clamp voltage
Output Short Circuit Current
R
L
= 100
(figure 5)
I
CL
= +18mA
V
IN
= V
DD
, V
OUT+
= 0V or
V
IN
= GND, V
OUT-
= 0V
EN = 0.8V and EN = 2.0 V,
V
OUT
= 0V or V
DD,
V
DD
= 3.6V
R
L
= 100 all channels
V
IN
= V
DD
or V
SS
(all inputs)
D
IN
= V
DD
or V
SS
EN = V
SS
, EN = V
DD
-10
-1.5
25
mV
V
9.0
mA
Output Three-State Current
+10
Loaded supply current, drivers
enabled
Loaded supply current, drivers
disabled
mA
18.0
mA
3.0
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25
o
C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages.
2. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
本帖最后由 dontium 于 2015-1-23 13:39 编辑 IntroductionNewer high-speed ADCs e outfittedwith a large analog-input bandwidth (aboutthree to six times the maximum samplingfrequency) ......
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