74ACT16245 16-Bit Transceiver with 3-STATE Outputs
August 1999
Revised May 2005
74ACT16245
16-Bit Transceiver with 3-STATE Outputs
General Description
The ACT16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. Each has
separate control inputs which can be shorted together for
full 16-bit operation. The T/R inputs determine the direction
of data flow through the device. The OE inputs disable both
the A and B ports by placing them in a high impedance
state.
Features
s
Bidirectional non-inverting buffers
s
Separate control logic for each byte
s
16-bit version of the ACT245
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT16245SSC
74ACT16245MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Description
Pin Names
OE
n
T/R
A
0
–A
15
B
0
–B
15
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs/Outputs
Side B Outputs/Inputs
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500296
www.fairchildsemi.com
74ACT16245
Functional Description
The ACT16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation. The following description
applies to each byte. When the T/R input is HIGH, then Bus
A data is transmitted to Bus B. When the T/R input is LOW,
Bus B data is transmitted to Bus A. The 3-STATE outputs
are controlled by an Output Enable (OE
n
) input for each
byte. When OE
n
is LOW, the outputs are in 2-state mode.
When OE
n
is HIGH, the outputs are in the high impedance
mode, but this does not interfere with entering new data
into the inputs.
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Outputs
T/R
1
L
H
X
Bus B
0
–B
7
Data to Bus A
0
–A
7
Bus A
0
–A
7
Data to Bus B
0
–B
7
HIGH-Z State on A
0
–A
7
, B
0
–B
7
Outputs
T/R
2
L
H
X
Bus B
8
–B
15
Data to Bus A
8
–A
15
Bus A
8
–A
15
Data to Bus B
8
–B
15
HIGH-Z State on A
8
–A
15
, B
8
–B
15
Logic Diagram
www.fairchildsemi.com
2
74ACT16245
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
V
O
V
O
0.5V to
7.0V
20 mA
20 mA
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
0.5V
V
CC
0.5V
0.5V
V
CC
0.5V
DC Output Diode Current (I
OK
)
40
q
C to
85
q
C
125 mV/ns
DC Output Voltage (V
O
)
DC Output Source/Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin
Storage Temperature
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH
Input Voltage
Maximum LOW
Input Voltage
Minimum HIGH
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW
Output Voltage
4.5
5.5
4.5
5.5
I
OZT
I
IN
I
CCT
I
CC
I
OLD
I
OHD
Maximum I/O
Leakage Current
Maximum Input
Leakage Current
Maximum I
CC
/Input
Max Quiescent
Supply Current
Minimum Dynamic
Output Current (Note 3)
5.5
5.5
5.5
5.5
5.5
0.6
8.0
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
V
I
OH
=
24 mA
I
OH
=
24 mA (Note 2)
V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
V
I
OL
= 24 mA
I
OL
= 24 mA (Note 2)
V
I
V
O
V
I
V
I
V
IN
V
OLD
V
OHD
V
IL
, V
IH
V
CC
, GND
V
CC
, GND
V
CC
2.1V
V
CC
or GND
1.65V Max
3.85V Min
r
0.5
r
0.1
r
5.0
r
1.0
1.5
80.0
75
P
A
P
A
mA
P
A
mA
mA
75
Note 2:
All outputs loaded; thresholds associated with output under test.
Note 3:
Maximum test duration 2.0 ms; one output loaded at a time.
3
www.fairchildsemi.com
74ACT16245
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation
Delay A
n
, B
n
to B
n
, A
n
Output Enable
Time
Output Disable
Time
5.0
5.0
Parameter
(V)
(Note 4)
5.0
Min
3.2
2.6
3.7
4.1
2.2
2.0
T
A
C
L
25
q
C
50 pF
Typ
5.7
5.1
6.4
7.4
5.4
5.2
Max
8.4
7.9
9.4
10.5
8.7
8.2
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
9.0
8.4
10.0
11.6
9.3
8.8
ns
ns
ns
Units
Min
3.2
2.6
2.7
3.4
2.2
2.0
Note 4:
Voltage Range 5.0 is 5.0V
r
0.5V.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Pin Capacitance
Power Dissipation Capacitance
Typ
4.5
25
Units
pF
pF
V
CC
V
CC
5.0V
5.0V
Conditions
www.fairchildsemi.com
4
74ACT16245
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
5
www.fairchildsemi.com
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
