74ACT1284 IEEE 1284 Transceiver
June 1996
Revised November 1999
74ACT1284
IEEE 1284 Transceiver
General Description
The 74ACT1284 contains four non-inverting bidirectional
buffers and three non-inverting buffers with open Drain out-
puts and high drive capability on the B Ports. It is intended
to provide a standard signaling method for a bi-direction
parallel peripheral in an Extended Capabilities Port mode
(ECP).
The HD (active HIGH) input pin enables the B Ports to
switch from open Drain to a high drive totem pole output,
capable of sourcing 14 mA on all seven buffers. The DIR
input determines the direction of data flow on the bidirec-
tional buffers. DIR (active HIGH) enables data flow from A
Ports to B Ports. DIR (active LOW) enables data flow from
B Ports to A Ports.
Features
s
TTL-compatible inputs
s
A Ports have standard 4 mA totem pole outputs
s
Typical input hysteresis of 0.5V
s
B Port high drive source/sink capability of 14 mA
s
Bidirectional non-inverting buffers
s
Supports IEEE P1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s
B Port outputs in High Impedance mode during power
down
s
Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number
74ACT1284SC
74ACT1284MSA
74ACT1284MTC
Package Number
M20B
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
HD
DIR
A
1
- A
4
B
1
- B
4
A
5
- A
7
B
5
- B
7
Description
High Drive Enable input (Active HIGH)
Direction Control Input
Side A Inputs or Outputs
Side B Inputs or Outputs
Side A Inputs
Side B Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS011683
www.fairchildsemi.com
74ACT1284
Absolute Maximum Ratings
(Note 3)
(Note 4)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
) A Side
DC Input Voltage (V
I
) B Side
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
) A Side
DC Output Voltage (V
O
) B Side
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
±
50 mA
−65°C
to
+150°C
±
50 mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−2V
to
+7V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−2V
to
+7V
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
4.7V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
Note 3:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
Note 4:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
4.7
4.7
V
OL
Maximum LOW Level
Output Voltage
4.7
I
IN
I
CCT
I
CC
I
OZ
I
OFF
∆
VT
R
D
Maximum Input
Leakage Current
Maximum I
CC
/Input
Maximum Quiescent
Supply Current
Maximum Output
Leakage Current
Maximum B-Side Power Down
Leakage Current
Input Hysteresis
Maximum Output Impedance
Minimum Output Impedance
0.4
0.4
0.4
V
5.5
5.5
5.5
5.5
0.0
5.0
5.0
5.0
400
±20
100
0.4
22
8
±0.1
1.5
400
±20
100
0.4
22
8
±1.0
1.5
500
±20
100
0.35
24
6
µA
mA
µA
µA
µA
V
Ω
Ω
4.7
3.7
2.4
0.2
3.7
2.4
0.2
3.7
2.4
0.2
V
V
V
CC
(V)
4.7
5.5
4.7
5.5
4.7
Guaranteed Limits
T
A
= +25°C
2.0
2.0
0.8
0.8
4.5
T
A
=
0°C to
+70°C
T
A
= −40°C
to
+85°C
2.0
2.0
0.8
0.8
4.5
2.0
2.0
0.8
0.8
4.5
V
Units
V
V
Conditions
Recognized
High Signal
Recognized
Low Signal
I
OUT
= −50 µA
(An)
V
IN
=
V
IL
or V
IH
(Note 5)
I
OH
= −4
mA (A
n
)
I
OH
= −14
mA (B
n
)
I
OUT
=
50
µA
(An)
V
IN
=
V
IL
or V
IH
(Note 5)
I
OH
=
4 mA (A
n
)
I
OH
=
14 mA (B
n
)
V
I
=
V
CC
, GND
(DIR, A5, A6, A7, HD)
V
I
=
V
CC
−
2.1V
V
IN
=
V
CC
or GND
V
O
=
V
CC
, GND
V
OUT
=
5.25V
V
T
+ −
V
T
−
B
n
(Note 6)
B
n
(Note 6)
Note 5:
All outputs loaded; thresholds on input associated with output under test.
Note 6:
This parameter is guaranteed but not tested, characterized only: RD is the measure of the B-Side output impedance with the output in the HIGH
state.
3
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74ACT1284
AC Loading and Waveforms
t
SLEW
measures between 10% to 90% on the t
PHL
Transition
FIGURE 1. A to B Direction Test Load and Waveforms
t
SLEW
measures between 10% to 90% on the t
PLH
Transition
FIGURE 2. B Output Test Load and Waveforms
FIGURE 3. B to A Direction Test Load and Waveforms for Outputs A
1
- A
4
FIGURE 4. A to B Direction Test Load and Waveforms for Open Drain B
1
- B
7
5
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