74ACQ374 • 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs
July 1989
Revised November 1999
74ACQ374 • 74ACTQ374
Quiet Series Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
The ACQ/ACTQ374 is a high-speed, low-power octal D-
type flip-flop featuring separate D-type inputs for each flip-
flop and 3-STATE outputs for bus-oriented applications. A
buffered Clock (CP) and Output Enable (OE) are common
to all flip-flops.
The ACQ/ACTQ374 utilizes FACT Quiet Series technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
Buffered positive edge-triggered clock
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard AC/ACT374
Ordering Code:
Order Number
74ACQ374SC
74ACQ374SJ
74ACQ374PC
74ACTQ374SC
74ACTQ374SJ
74ACTQ374QSC
74ACTQ374PC
Package Number
M20B
M20D
N20A
M20B
M20D
MQA20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
Description
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010238
www.fairchildsemi.com
74ACQ374 • 74ACTQ374
Logic Symbols
Functional Description
The ACQ/ACTQ374 consists of eight edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D-type inputs that meet the setup
and hold time requirements on the LOW-to-HIGH Clock
(CP) transition. With the Output Enable (OE) LOW, the
contents of the eight flip-flops are available at the outputs.
When the OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops.
IEEE/IEC
Truth Table
Inputs
D
n
H
L
X
CP
Outputs
OE
L
L
H
O
n
H
L
Z
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACQ374 • 74ACTQ374
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or Sink Current
Junction Temperature (T
J
)
PDIP
140°C
±50
mA
−65°C
to
+150°C
±300
mA
±50
mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
ACQ
ACTQ
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆V/∆t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate
∆V/∆t
ACTQ devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics for ACQ
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 4)
I
OLD
I
OHD
I
OZ
Maximum Input Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum 3-STATE
Leakage Current
V
OLP
Quiet Output
Maximum Dynamic V
OL
5.5
5.0
1.1
±0.25
1.5
±2.5
µA
V
5.5
5.5
5.5
5.5
4.0
0.002
0.001
0.001
T
A
= +25°C
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
V
IN
=
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
−75
40.0
µA
mA
mA
µA
V
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
Figure 1, Figure 2
(Note 5)(Note 6)
V
I
OUT
=
50
µA
V
I
OH
= −12
mA
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
V
I
OUT
= −50 µA
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
Units
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
I
CC
(Note 4) Maximum Quiescent Supply Current
3
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74ACQ374 • 74ACTQ374
DC Electrical Characteristics for ACQ
Symbol
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.0
5.0
3.1
1.9
V
CC
(V)
5.0
Typ
−0.6
(Continued)
T
A
= −40°C
to
+85°C
Guaranteed Limits
−1.2
V
Figure 1, Figure 2
(Note 5)(Note 6)
3.5
1.5
V
V
(Note 5)(Note 7)
(Note 5)(Note 7)
T
A
= +25°C
Units
Conditions
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 5:
DIP Package.
Note 6:
Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
Note 7:
Max number of data inputs (n) switching. (n−1) inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
(Note 4) Maximum Input Leakage Current
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
(Note 4)
V
OLP
V
OLV
V
IHD
V
ILD
Maximum 3-STATE
Current
Maximum
I
CC
/Input (Note 4)
Minimum Dynamic
Output Current (Note 8)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
1.2
4.0
1.5
−1.2
2.2
0.8
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
±0.25
2.0
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±2.5
1.5
75
−75
40.0
µA
µA
mA
mA
mA
µA
V
V
V
V
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 8)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 8)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figure 1, Figure 2
(Note 10)(Note 11)
Figure 1, Figure 2
(Note 10)(Note 11)
(Note 10)(Note 12)
(Note 10)(Note 12)
Note 8:
All outputs loaded; thresholds on input associated with output under test.
Note 9:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 10:
DIP package.
Note 11:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND
Note 12:
Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
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4
74ACQ374 • 74ACTQ374
AC Electrical Characteristics for ACQ
V
CC
Symbol
f
MAX
t
PLH
t
PHL
t
PZL
t
PZH
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output Skew (Note 14)
CP to O
n
Voltage Range 3.3 is 3.3V
±
0.3V
Note 14:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
T
A
= +25°C
C
L
=
50 pF
Min
75
90
3.0
2.0
3.0
2.0
1.0
1.0
9.5
6.5
9.5
6.5
9.5
8.0
1.0
0.5
13.0
8.5
13.0
8.5
14.5
9.5
1.5
1.0
Typ
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
70
85
3.0
2.0
3.0
2.0
1.0
1.0
13.5
9.0
13.5
9.0
15.0
10.0
1.5
1.0
Max
MHz
ns
ns
ns
ns
Units
Parameter
Maximum Clock
Frequency
Propagation Delay
CP to O
n
Output Enable Time
Output Disable Time
(V)
(Note 13)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Note 13:
Voltage Range 5.0 is 5.0V
±
0.5V
AC Operating Requirements for ACQ
V
CC
Symbol
Parameter
(V)
(Note 15)
t
S
t
H
t
W
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
CP Pulse Width,
HIGH or LOW
Note 15:
Voltage Range 5.0 is 5.0V
±
0.5V
Voltage Range 3.3 is 3.3V
±
0.3V
T
A
= +25°C
C
L
=
50 pF
Typ
0
0
0
2.0
2.0
2.0
3.0
3.0
1.5
1.5
4.0
4.0
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
3.0
3.0
1.5
1.5
4.0
4.0
ns
ns
ns
Units
3.3
5.0
3.3
5.0
3.3
5.0
AC Electrical Characteristics for ACTQ
V
CC
Symbol
f
MAX
t
PLH
t
PHL
t
PZL
t
PZH
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Parameter
Maximum Clock
Frequency
Propagation Delay
CP to O
n
Output Enable Time
Output Disable Time
Output to Output Skew (Note 17)
CP to O
n
(V)
(Note 16)
5.0
5.0
5.0
5.0
5.0
Min
85
2.0
2.0
1.0
7.0
7.5
8.0
0.5
9.0
9.0
10.0
1.0
T
A
= +25°C
C
L
=
50 pF
Typ
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
80
2.0
2.0
1.0
9.5
9.5
10.5
1.0
Max
MHz
ns
ns
ns
ns
Units
Note 16:
Voltage Range 5.0 is 5.0V
±
0.5V
Note 17:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
5
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