XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
JULY 2008
REV. 1.0.1
GENERAL DESCRIPTION
The XR20V2172
1
(V2172) is a high performance two
channel universal asynchronous receiver and
transmitter (UART) with 64 byte TX and RX FIFOs, a
selectable I
2
C/SPI slave interface and RS232
transceiver. The V2172 operates from 3.3 to 5.5 volts.
The enhanced features in the V2172 include a
programmable fractional baud rate generator, an 8X
and 4X sampling rate that allows for a maximum baud
rate of 1 Mbps at 3.3V. The standard features include
16 selectable TX and RX FIFO trigger levels,
automatic hardware (RTS/CTS) and software (Xon/
Xoff) flow control, and a complete modem interface.
Onboard registers provide the user with operational
status and data error flags. An internal loopback
capability allows system diagnostics. The V2172 is
available in the 64-pin QFN.
N
OTE
:
1 Covered by U.S. Patent #5,649,122
FEATURES
•
Selectable I
2
C/SPI Interface
•
Meets true EIA/TIA-232-F Standards from +3.3V to
+5.5V operation
•
Data rate up to 1 Mbps
•
45us sleep mode exit (charge pump to full power)
•
ESD protection for RS-232 I/O pins at
■
■
■
+/-15kV - Human Body Model
+/-15kV - IEC 61000-4-2, Air-Gap Discharge
+/- 8kV - IEC 61000-4-2, Contact Discharge
Fractional Baud Rate Generator
Transmit and Receive FIFOs of 64 bytes
16 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Halt and Resume Transmission Control
Automatic sleep mode
General Purpose I/Os
Full modem interface
•
Full-featured UART
■
■
■
■
■
■
■
■
■
APPLICATIONS
•
Portable Appliances
•
Battery-Operated Devices
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR20V2172 B
LOCK
D
IAGRAM
XTAL1
XTAL2
VCC
•
64-QFN packages
R_EN
GND
FAST
ACP
C2+
C1+
C2-
C1-
VR EF+
IR Q #
RESET#
C rys ta l
O sc /B u ffe r
BRG
TXA
RXA
5K
C h a rg e P u m p
VR EF-
TXDA
RXDA
RTSA
DTRA
CTSA
DSRA
R IA
CDA
CDB
R IB
DSRB
CTSB
DTRB
RTSB
TXDB
RXDB
TXB
RXB
UART Registers
6 4 B yte
TX & RX
F IF O
RTSA#
DTRA#
CTSA#
5K
I2 C /S P I#
I2C/SPI Interface
SDA
SCK
A 0 /C S A #
A 1 /S I
SO
M odem
I/O s
DSRA#
5K
R IA #
5K
CDA#
C hannel A
CDB#
R IB #
DSRB#
CTSB#
D TR B#
RTSB#
TXB
RXB
C h A T ra n sc e iv e r
5K
C hannel B
C hannel B
T ra n sc e ive r
RXB_SEL
UART
R S -2 3 2 T ra n s ce iv e r
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
REV. 1.0.1
I2C/SPI#
RESET#
A0/CS#
CDA
VREF+
CTSA
A1/SI
CDB
VCC
N.C.
64
60
56
54
52
62
61
59
57
55
51
58
53
50
GND
SDA
N.C.
CTSB
RTSB
RXB_SEL
RXB
TXB
N.C.
N.C.
N.C.
DTRB
RIB
DSRB
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21
29
23
22
25
26
27
28
30
31
XTAL2 17
18
FAST 19
20
24
32
63
49
N.C.
C1+
RIA
C1-
SO
C3
48
47
46
45
44
43
N.C.
N.C.
N.C.
VCC
C2+
C2-
TXDA
DTRA
DSRA
RXDA
IRQ#
N.C.
N.C.
GND
N.C.
SCK
XR20V2172
64-pin QFN
42
41
40
39
38
37
36
35
34
33
N.C.
N.C.
VREF-
ORDERING INFORMATION
P
ART
N
UMBER
XR20V2172IL64
P
ACKAGE
64-pin QFN
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
D
EVICE
S
TATUS
Active
2
RXDB
N.C.
N.C.
TXDB
R_EN
RTSA
GND
ACP
N.C.
N.C.
N.C.
XR20V2172
REV. 1.0.1
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
PIN DESCRIPTIONS
Pin Description
N
AME
I2C (SPI) INTERFACE
I
2
C/SPI#
61
I/O
I
2
C-bus or SPI interface select. I
2
C-bus interface is selected if this pin is
HIGH. SPI interface is selected if this pin is LOW. This pin is not 5V toler-
ant.
I
2
C-bus data input/output (open-drain). If SPI configuration is selected,
then this pin is undefined and must be connected to VCC. This pin is not
5V tolerant.
I
2
C-bus or SPI serial input clock.
When the I
2
C-bus interface is selected, the serial clock idles HIGH. When
the SPI interface is selected, the serial clock idles LOW. This pin is not 5V
tolerant.
I
2
C-bus device address select A0 or SPI chip select. If I
2
C-bus configura-
tion is selected, this pin along with the A1 pin allows user to change the
device’s base address. If SPI configuration is selected, this pin is the SPI
chip select pin (Schmitt-trigger, active LOW). This pin is not 5V tolerant.
I
2
C-bus device address select A1 or SPI data input pin. If I
2
C-bus onfigu-
ration is selected, this pin along with A0 pin allows user to change the
device’s base address. If SPI configuration is selected, this pin is the SPI
data input pin. This pin is not 5V tolerant.
SPI data output pin. If SPI configuration is selected then this pin is a
three-stateable output pin. If I
2
C-bus configuration is selected, this pin is
undefined and must be left unconnected.
Interrupt output (open-drain, active LOW).
Reset (active LOW) - A longer than 40 ns LOW pulse on this pin will reset
the internal registers and all outputs. The UART transmitter output will be
idle and the receiver input will be ignored. This pin is not 5V tolerant.
64-QFN
P
IN
#
T
YPE
D
ESCRIPTION
SDA
2
I/O
SCK
33
I
A0/
CS#
57
I
A1/
SI
59
I
SO
64
O
IRQ#
RESET#
38
52
OD
I
SERIAL I/O INTERFACE (CMOS/TTL Voltage Levels)
RXB
TXB
7
8
I
O
UART Channel B Receive Data. This pin can be used to communicate
with external IR or RS-232 transceiver. This pin is not 5V tolerant.
UART Channel B Transmit Data. This pin can be used to communicate
with external IR or RS-232 transceiver.
MODEM OR SERIAL I/O INTERFACE (EIA-232/RS-232 Voltage Levels)
RXDA
RXDB
TXDA
TXDB
RTSA
RTSB
CTSA
CTSB
39
29
42
27
28
5
63
4
I
UART Receive Data. UART receive data input must idle LOW (< 1.5V).
This input has an internal pull-down resistor and can be left unconnected
when not used.
UART Transmit Data. The TX signal will be LOW (< 1.5V) during reset or
idle (no data).
UART Request-to-Send. This output must be asserted prior to using auto
RTS flow control, see EFR[6], MCR[1] and IER[6].
UART Clear-to-Send. It can be used for auto CTS flow control, see
EFR[7], MSR[4] and IER[7]. This input has an internal pull-down resistor
and can be left unconnected when not used.
O
O
I
3
XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
Pin Description
N
AME
DTRA
DTRB
DSRA
DSRB
CDA
CDB
RIA
RIB
64-QFN
P
IN
#
41
12
40
14
60
62
58
13
T
YPE
O
D
ESCRIPTION
UART Data-Terminal-Ready. See MCR[0].
REV. 1.0.1
I
UART Data-Set-Ready. This input has an internal pull-down resistor and
can be left unconnected when not used. See MSR[5].
UART Carrier-Detect. This input has an internal pull-down resistor and
can be left unconnected when not used. See MSR[7].
UART Ring-Indicator. This input has an internal pull-down resistor and
can be left unconnected when not used. See MSR[6].
I
I
Ancillary signals (CMOS/TTL Voltage Levels)
XTAL1
XTAL2
ACP
15
17
24
I
O
I
Crystal or external clock input. This pin is not 5V tolerant.
Crystal or buffered clock output.
Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the
charge pump is shut off if the V2172 is already in partial sleep mode, i.e.
the crystal oscillator is stopped. This pin is 5V tolerant.
When FAST is HIGH, the maximum serial data rate is 1 Mbps.
When FAST is LOW, the maximum serial data rate is 250 Kbps. This pin
is 5V tolerant.
When the supply voltage is < 3.6V, connect R_EN to VCC.
When the supply voltage is > 3.6V, connect R_EN to GND. This pin is 5V
tolerant.
When RXB_SEL is HIGH, RXB is the receive data input.
When RXB_SEL is LOW, RXDB is the receive data input. This pin is 5V
tolerant.
Charge pump capacitors. As shown in
Figure 1,
a 0.1 uF capacitor
should be placed between these 2 pins.
Charge pump capacitors. As shown in
Figure 1,
a 0.1 uF capacitor
should be placed between these 2 pins.
When the supply voltage is 3.3 V, C3 should be connected to VCC.
When the supply voltage is 5 V, C3 should be connected to a 1 uF capac-
itor to GND.
-5.0V generated by the charge pump.
+5.0V generated by the charge pump.
Power supply common, ground.
3.3 to 5.5V power supply.
FAST
19
I
R_EN
20
I
RXB_SEL
6
I
C2+
C2-
C1+
C1-
C3
44
43
51
50
56
-
-
-
VREF-
VREF+
GND
VCC
25
53
1, 16, 21, 35
45, 54
Pwr
Pwr
Pwr
Pwr
4
XR20V2172
REV. 1.0.1
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
Pin Description
N
AME
-
64-QFN
P
IN
#
PAD
T
YPE
Pwr
D
ESCRIPTION
The center pad on the backside of the QFN packages is metallic and is
not electrically connected to anything inside the device. It must be sol-
dered on to the PCB and may be optionally connected to GND on the
PCB. The thermal pad size on the PCB should be the approximate size of
this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB
thermal pad.
No Connection.
NC
3, 9, 10, 11, 18,
22, 23, 26, 30,
31, 32, 34, 36,
37, 46, 47, 48,
49, 55
-
N
OTE
:
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH" indicates a voltage in the range VIH to VCC. For RS-232
input voltage levels, ’LOW’ is any voltage < -3V and ’HIGH’ is any voltage > 3V. For RS-232 output voltage levels,
’LOW’ is any voltage < -5V and ’HIGH’ is any voltage > 5V.
5
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