XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
JULY 2008
REV. 1.0.1
GENERAL DESCRIPTION
The XR17V258
1
(V258) is a single chip 8-channel
66MHz PCI (Peripheral Component Interconnect)
UART (Universal Asynchronous Receiver and
Transmitter)
solution,
optimized
for
higher
performance and lower power. The V258 device with
its fifth generation register set is designed to meet the
high
bandwidth
and
power
management
requirements for multi-serial communication ports for
system administration and management. The 32-bit
66MHz PCI interface is compliant with PCI 3.0 and
PCI power management revision 1.1 specifications.
The device provides an upgrade path for Exar’s
33MHz 5V and Universal PCI UART family of
products in a 144-pin LQFP package.
The V258 consists of eight independent UART
channels, each with set of configuration and
enhanced registers, 64 bytes of Transmit (TX) and
Receive (RX) FIFOs, and a fractional Baud Rate
Generator (BRG). A global interrupt source register
provides a complete interrupt status indication for all
8-channels to speed up interrupt parsing. The V258
device operates at 33/66MHz and features fully
programmable TX and RX FIFO level triggers,
automatic hardware and software flow control, and
automatic RS-485 half duplex direction control output
for software and hardware design simplification.
N
OTE
1:
Covered by U.S. Patents #5,649,122 and #5,949,787
•
Factory Automation and Process Control
•
Instrumentation
•
Multi-port RS-232/RS-422/RS-485 Cards
•
Point-of-Sale Systems
FEATURES
•
High performance 32-bit 66MHz PCI UART
•
PCI 3.0 compliance
•
PCI power management rev. 1.1 compliance
•
EEPROM interface for PCI configuration
•
3.3V supply with 5V tolerant non-PCI (serial) inputs
•
Data read/write burst operation
•
Global interrupt register for all eight UART channels
•
Up to 8 Mbps serial data rate
•
Eight multi-purpose inputs/outputs
•
A 16-bit general purpose timer/counter
•
Sleep mode with wake-up Indicator
•
Eight independent UART channels controlled with
■
■
■
■
■
■
■
■
APPLICATIONS
•
Remote Access Servers
•
Storage Network Management
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XR17V258
16C550 compatible register Set
64-byte TX and RX FIFOs with level counters
and programmable trigger levels
Fractional baud rate generator
Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
Automatic Xon/Xoff software flow control
RS-485 half duplex direction control output
with selectable turn-around delay
Infrared (IrDA 1.0) data encoder/decoder
Programmable data rate with prescaler
AD [31 :0]
C /B E#[3:0]
U AR T C h an nel 0
64-b yte TX FIFO
UA RT
Re gs
TX & RX
IR
EN D E C
T X[7:0]
R X[7:0]
P AR
F R AM E #
T R D Y#
IR D Y#
S T OP #
D E VS E L #
ID S E L #
33/66M H z CL K
R ST#
P E RR #
S E RR #
IN T A#
PME#
E N IR
E E CK
EEDI
EEDO
E E CS
C onfiguration
Space
R e giste rs
16-bit
T ime r/C ounte r
BR G 64-b yte RX FIFO
R TS#[7:0]
PC I L o ca l
Bu s
Int erfa ce
Global
C o n fig u ratio n
R eg isters
U AR T C h an nel 1
D TR #[7:0]
U AR T C h an nel 2
C TS #[7:0]
U AR T C h an nel 3
U AR T C h an nel 4
U AR T C h an nel 5
U AR T C h an nel 6
R I#[7:0]
D SR #[7:0]
D CD #[7:0]
U AR T C h an nel 7
M u lti-p u rp o se
In p u ts/Ou tp u ts
C rystal Osc/B u ffer
M PIO [7:0]
E E PR OM
In terface
X T AL 1/C L K
X T AL 2
T MR C K
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
F
IGURE
2. P
IN
O
UT OF THE
D
EVICE
DSR4#
DTR3#
101 DSR2#
DSR3#
100 CTS2#
79 DTR5#
DSR5#
DTR2#
DTR4#
MPIO0
MPIO1
CTS4#
RTS2#
RTS3#
CTS3#
RTS5#
86 RTS4#
MPIO2
CD2#
CD3#
CD4#
CD5#
MPIO3
GND
VCC
REV. 1.0.1
103 RI2#
RI3#
RI4#
RX2
107
104
91 RX3
99
98
97
96
95
94
93
92
90
89
88
87
85
84
83
82
81
RX4
108
106
105
102
80
78
77
RI5#
TX2
TX3
TX4
TX5
76
75
74
XTAL2 109
XTAL1 110
PME#
VCC
111
112
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
CTS5#
RX5
ENIR
TMRCK
MPIO4
MPIO5
MPIO6
MPIO7
VCC
GND
TX6
DTR6#
RTS6#
RI6#
CD6#
DSR6#
CTS6#
RX6
TX7
DTR7#
RTS7#
RI7#
CD7#
DSR7#
CTS7#
RX7
GND
VCC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
EEDO 113
EEDI
EECS
EECK
TX1
114
115
116
117
DTR1# 118
RTS1# 119
RI1#
CD1#
120
121
DSR1# 122
CTS1# 123
RX1
TX0
124
125
DTR0# 126
RTS0# 127
RI0#
CD0#
128
129
XR17V258
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
31
27
32
35
GND
33
DSR0# 130
CTS0# 131
RX0
INTA#
RST#
CLK
GND
VCC
AD31
AD30
AD29
AD28
AD27
AD26
AD25
132
133
134
135
136
137
138
139
140
141
142
143
144
11
12
17
DEVSEL# 18
19
20
STOP# 21
24
CBE1 25
28
29
PERR# 22
SERR# 23
10
13
CBE2 14
FRAME# 15
IRDY# 16
26
30
34
36
1
2
4
3
5
6
7
8
9
IDSEL
CBE3
TRDY#
GND
AD21
AD18
AD14
AD13
AD12
AD11
ORDERING INFORMATION
P
ART
N
UMBER
XR17V258IV
P
ACKAGE
144-Lead LQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
D
EVICE
S
TATUS
Active
2
CBE0
AD24
AD23
AD17
AD22
AD20
AD19
AD16
AD15
AD10
VCC
GND
VCC
PAR
AD9
AD8
VCC
XR17V258
REV. 1.0.1
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
PIN DESCRIPTIONS
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
PCI LOCAL BUS INTERFACE
RST#
134
I
PCI bus reset input (active LOW). It resets the PCI local bus configuration
space registers, device configuration registers and UART channel registers to
the default condition.
PCI bus clock input of up to 66.67MHz.
Address data lines [31:0] (bidirectional).
CLK
AD31-AD25,
AD24,
AD23-AD16,
AD15-AD8,
AD7-AD0
FRAME#
C/BE0#-
C/BE3#
IRDY#
135
138-144,
1,
6-13,
26-33,
37-44
15
36,25,14,2
I
IO
I
I
Bus transaction cycle frame (active LOW). It indicates the beginning and
duration of an access.
Bus command/byte enable [3:0] (active LOW). This line is multiplexed for bus
command during the address phase and byte enables during the data phase.
Initiator ready (active LOW). During a write, it indicates that valid data is
present on data bus. During a read, it indicates the master is ready to accept
data.
Target ready (active LOW).
Target request to stop current transaction (active LOW).
Initialization device select (active HIGH).
Device select to the XR17V258 (active LOW).
Device interrupt from XR17V258 (open drain, active LOW).
Power Management Event signal. While in D3
hot
state, if the PME_Enable bit
in the Power Management Control/Status Register is set, the V258 asserts
the PME# upon receiving a new character or upon change of state of modem
inputs on any channel.
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active HIGH).
Data parity error indicator, except for special cycle transactions (active LOW).
Optional in bus target application.
System error indicator, Address parity or data parity during special cycle
transactions (open drain, active LOW). Optional in bus target application.
16
I
TRDY#
STOP#
IDSEL
DEVSEL#
INTA#
PME#
17
21
3
18
133
111
O
O
I
O
OD
OD
PAR
PERR#
SERR#
24
22
23
IO
O
OD
MODEM OR SERIAL I/O INTERFACE
TX0
RX0
125
132
O
I
UART channel 0 Transmit Data or infrared transmit data.
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted internally prior to
decoding by setting FCTR bit [4].
UART channel 0 Request to Send or general purpose output (active LOW).
UART channel 0 Clear to Send or general purpose input (active LOW).
RTS0#
CTS0#
127
131
O
I
3
XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.1
PIN DESCRIPTIONS
N
AME
DTR0#
DSR0#
CD0#
RI0#
TX1
RX1
P
IN
#
126
130
129
128
117
124
T
YPE
O
I
I
I
O
I
D
ESCRIPTION
UART channel 0 Data Terminal Ready or general purpose output (active
LOW).
UART channel 0 Data Set Ready or general purpose input (active LOW).
UART channel 0 Carrier Detect or general purpose input (active LOW).
UART channel 0 Ring Indicator or general purpose input (active LOW).
UART channel 1 Transmit Data or infrared transmit data.
UART channel 1 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 1 Request to Send or general purpose output (active LOW).
UART channel 1 Clear to Send or general purpose input (active LOW).
UART channel 1 Data Terminal Ready or general purpose output (active
LOW).
UART channel 1 Data Set Ready or general purpose input (active LOW).
UART channel 1 Carrier Detect or general purpose input (active LOW).
UART channel 1 Ring Indicator or general purpose input (active LOW).
UART channel 2 Transmit Data or infrared transmit data.
UART channel 2 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 2 Request to Send or general purpose output (active LOW).
UART channel 2 Clear to Send or general purpose input (active LOW).
UART channel 2 Data Terminal Ready or general purpose output (active
LOW).
UART channel 2 Data Set Ready or general purpose input (active LOW).
UART channel 2 Carrier Detect or general purpose input (active LOW).
UART channel 2 Ring Indicator or general purpose input (active LOW).
UART channel 3 Transmit Data or infrared transmit data.
UART channel 3 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 3 Request to Send or general purpose output (active LOW).
UART channel 3 Clear to Send or general purpose input (active LOW).
UART channel 3 Data Terminal Ready or general purpose output (active
LOW).
UART channel 3 Data Set Ready or general purpose input (active LOW).
UART channel 3 Carrier Detect or general purpose input (active LOW).
RTS1#
CTS1#
DTR1#
DSR1#
CD1#
RI1#
TX2
RX2
119
123
118
122
121
120
106
99
O
I
O
I
I
I
O
I
RTS2#
CTS2#
DTR2#
DSR2#
CD2#
RI2#
TX3
RX3
104
100
105
101
102
103
98
91
O
I
O
I
I
I
O
I
RTS3#
CTS3#
DTR3#
DSR3#
CD3#
96
92
97
93
94
O
I
O
I
I
4
XR17V258
REV. 1.0.1
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
PIN DESCRIPTIONS
N
AME
RI3#
TX4
RX4
P
IN
#
95
88
81
T
YPE
I
O
I
D
ESCRIPTION
UART channel 3 Ring Indicator or general purpose input (active LOW).
UART channel 4 Transmit Data or infrared transmit data.
UART channel 4 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 4 Request to Send or general purpose output (active LOW).
UART channel 4 Clear to Send or general purpose input (active LOW).
UART channel 4 Data Terminal Ready or general purpose output (active
LOW).
UART channel 4 Data Set Ready or general purpose input (active LOW).
UART channel 4 Carrier Detect or general purpose input (active LOW).
UART channel 4 Ring Indicator or general purpose input (active LOW).
UART channel 5 Transmit Data or infrared transmit data.
UART channel 5 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 5 Request to Send or general purpose output (active LOW).
UART channel 5 Clear to Send or general purpose input (active LOW).
UART channel 5 Data Terminal Ready or general purpose output (active
LOW).
UART channel 5 Data Set Ready or general purpose input (active LOW).
UART channel 5 Carrier Detect or general purpose input (active LOW).
UART channel 5 Ring Indicator or general purpose input (active LOW).
UART channel 6 Transmit Data or infrared transmit data.
UART channel 6 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 6 Request to Send or general purpose output (active LOW).
UART channel 6 Clear to Send or general purpose input (active LOW).
UART channel 6 Data Terminal Ready or general purpose output (active
LOW).
UART channel 6 Data Set Ready or general purpose input (active LOW).
UART channel 6 Carrier Detect or general purpose input (active LOW).
UART channel 6 Ring Indicator or general purpose input (active LOW).
UART channel 7 Transmit Data or infrared transmit data.
RTS4#
CTS4#
DTR4#
DSR4#
CD4#
RI4#
TX5
RX5
86
82
87
83
84
85
80
71
O
I
O
I
I
I
O
I
RTS5#
CTS5#
DTR5#
DSR5#
CD5#
RI5#
TX6
RX6
78
72
79
75
76
77
62
55
O
I
O
I
I
I
O
I
RTS6#
CTS6#
DTR6#
DSR6#
CD6#
RI6#
TX7
60
56
61
57
58
59
54
O
I
O
I
I
I
O
5
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