XR16M680
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
SEPTEMBER 2008
REV. 1.0.0
GENERAL DESCRIPTION
The XR16M680
1
(M680) is an enhanced Universal
Asynchronous Receiver and Transmitter (UART) with
32 bytes of transmit and receive FIFOs, selectable
transmit and receive FIFO trigger levels, automatic
hardware and software flow control, and data rates of
up to 16 Mbps at 3.3V, 12.5 Mbps at 2.5V and 7.5
Mbps at 1.8V with 4X data sampling rate.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection
increases the performance by simplifying the
software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. Power consumption of the
M680 can be minimized by enabling the sleep mode
and PowerSave mode.
The M680 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M680 is available in 32-pin
QFN, 48-pin TQFP and 25-pin BGA packages. All
three packages offer both the 16 mode (Intel bus)
interface and the 68 mode (Motorola bus) interface
which allows easy integration with Motorola
processors.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
Pin-to-pin compatible with XR16L580 in 32-QFN
and 48-TQFP packages
•
Intel or Motorola Bus Interface select
•
16Mbps maximum data rate
•
Selectable TX/RX trigger levels
•
TX/RX FIFO Level Counters
•
Independent TX/RX Baud Rate Generator
•
Fractional Baud Rate Generator
•
Auto RTS/CTS Hardware Flow Control
•
Auto XON/XOFF Software Flow Control
•
Auto RS-485 Half-Duplex Direction Control
•
Multidrop mode w/ Auto Address Detect
•
Sleep Mode with Automatic Wake-up
•
PowerSave mode
•
Infrared (IrDA 1.0 and 1.1) mode
•
1.62V to 3.63V supply operation
•
Crystal oscillator or external clock input
APPLICATIONS
•
Personal Digital Assistants (PDA)
•
Cellular Phones/Data Devices
•
Battery-Operated Devices
•
Global Positioning System (GPS)
•
Bluetooth
F
IGURE
1. XR16M680 B
LOCK
D
IAGRAM
Pw rSave
A2:A0
D7:D0
IOR#
IOW # (R/W #)
CS#
INT (IRQ#)
RESET
(RESET#)
UART
Regs
UART
32 Byte TX FIFO
TX &
RX
IR
ENDEC
VCC
(1.62 to 3.63 V)
G ND
TX, RX,
RTS#, CTS#,
DTR#, DSR#,
RI#, CD#
Intel or
M otorola
Data Bus
Interface
BRG
32 Byte RX FIFO
16/68#
Crystal Osc/Buffer
XTAL1
XTAL2
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16M680
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
F
OR
32-
PIN
QFN
AND
48-
PIN
TQFP P
ACKAGES
I
N
16
AND
68 M
ODE
REV. 1.0.0
24 23 22 21 20 19 18 17
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
NC
NC
IOR #
GND
IOW #
XTAL 2
XTAL 1
PwrSave
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
25
26
27
28
29
30
31
32
CTS#
RESET
DTR#
RTS#
INT
A0
A1
A2
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
NC
NC
IOR#
GND
R/W#
XTAL 2
XTAL 1
PwrSave
CTS#
RESET#
DTR#
RTS#
IRQ#
A0
A1
A2
32- pin QFN in
Intel Bus Mode
32-pin QFN in
Motorola Bus
Mode
VCC
1 2 3 4 5 6 7 8
D4
16/68#
D5
D6
D7
RX
TX
CS
1 2 3 4 5 6 7 8
D4
16/68#
D5
D6
D7
RX
TX
CS#
GND
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
39
40
41
42
43
44
45
46
47
48
1 2
3
4
5
6
7
8
23
22
21
20
19
18
17
16
15
14
13
9 10 11 12
VCC
NC
CTS#
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
D4
NC
36 35 34 33 32 31 30 29 28 27 26 25
24
37
38
39
40
41
42
43
44
45
46
47
48
1 2
3
4
5
6
7
8
23
22
21
20
NC
RESET#
NC
DTR#
RTS#
NC
IRQ#
NC
A0
A1
A2
NC
NC
NC
NC
NC
NC
IOR#
GND
NC
IOW#
XTAL2
XTAL1
PwrSave
NC
CTS#
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
D4
NC
NC
RESET
NC
DTR#
RTS#
NC
INT
NC
A0
A1
A2
NC
48-TQFP in
Intel Bus Mode
19
18
17
16
15
14
48-TQFP in
Motorola Bus Mode
13
9 10 11 12
NC
NC
NC
NC
NC
IOR#
GND
VCC
NC
R/W#
XTAL2
XTAL1
PwrSave
16/68#
D5
D6
D7
NC
NC
RX
TX
NC
NC
CS#
NC
VCC
GND
2
16/68#
D5
D6
D7
NC
NC
RX
TX
NC
NC
CS#
NC
XR16M680
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
F
IGURE
3. P
IN
O
UT
A
SSIGNMENT
F
OR
25-
PIN
BGA P
ACKAGE
A1 Corner
1 2
A
B
C
D
E
Transparent Top View
CTS#
VCC
D0
D3
D4
RESET
16/68#
D6
D1
D2
INT
RTS#
D7
TX
D5
A1
A0
PwrSave
CS#
RX
A2
IOR#
IOW#
XTAL1
GND
3 4
5
ORDERING INFORMATION
P
ART
N
UMBER
XR16M680IL32
XR16M680IM48
XR16M680IB25
P
ACKAGE
32-pin QFN
48-Lead TQFP
25-Pin BGA
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
3
XR16M680
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
REV. 1.0.0
PIN DESCRIPTIONS
Pin Description
N
AME
32-QFN 48-TQFP 25-BGA
P
IN
#
P
IN
#
PIN#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
17
18
19
5
4
3
1
32
31
30
29
14
26
27
28
4
3
2
47
46
45
44
43
19
A5
A4
B4
C3
C2
E3
E1
D1
E2
D2
C1
B5
I
Address lines [2:0]. These 3 address lines select the internal regis-
ters in UART channel during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input should be connected to VCC.
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
This input is chip select (active low) to enable the device.
IOW#
(R/W#)
12
16
C5
I
CS#
INT
(IRQ#)
8
20
11
30
D4
A3
I
O
When 16/68# pin is at logic 1 for Intel bus interface, this output
(OD) become the active high device interrupt output. The output state is
defined by the user through the software setting of MCR[3]. INT is
set to the active mode when MCR[3] is set to a logic 1. INT is set to
the three state mode when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes the active low device interrupt output (open drain). An
external pull-up resistor is required for proper operation.
MODEM OR SERIAL I/O INTERFACE
TX
7
8
D3
O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
4
XR16M680
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
Pin Description
N
AME
RX
32-QFN 48-TQFP 25-BGA
P
IN
#
PIN#
P
IN
#
6
7
E4
T
YPE
I
D
ESCRIPTION
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6].
UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
UART Data-Terminal-Ready (active low) or general purpose output.
UART Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used.
UART Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used.
UART Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used.
RTS#
21
32
B3
O
CTS#
24
38
A1
I
DTR#
DSR#
CD#
RI#
22
25
26
27
33
39
40
41
-
-
-
-
O
I
I
I
ANCILLARY SIGNALS
XTAL1
XTAL2
PwrSave
10
11
9
14
15
13
D5
-
C4
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Power-Save (active high). This feature isolates the M680’s data bus
interface from the host preventing other bus activities that cause
higher power drain during sleep mode. See Sleep Mode with Auto
Wake-up and Power-Save Feature section for details. This pin does
not have an internal pull-down resistor. This input should be con-
nected to GND when not used.
Intel or Motorola Bus Select. When 16/68# pin is at logic 1, 16 or
Intel Mode, the device will operate in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface. This pin does not
have an internal pull-up or pull-down resistor.
When 16/68# pin is at logic 1 for Intel bus interface, this input
becomes RESET (active high). When 16/68# pin is at logic 0 for
Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal reg-
isters and all outputs of the UART. The UART transmitter output will
be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period (see UART Reset Conditions).
1.62V to 3.63V power supply.
Power supply common, ground.
The center pad on the backside of the QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on
the PCB should be the approximate size of this center pad and
should be solder mask defined. The solder mask opening should be
at least 0.0025" inwards from the edge of the PCB thermal pad.
16/68#
2
1
B2
I
RESET
(RESET#)
23
35
A2
I
VCC
GND
GND
28
13
Center
Pad
42
18
-
B1
E5
-
Pwr
Pwr
Pwr
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
