XR16M670
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
SEPTEMBER 2008
REV. 1.0.0
GENERAL DESCRIPTION
The XR16M670
1
(M670) is an enhanced Universal
Asynchronous Receiver and Transmitter (UART) with
32 bytes of transmit and receive FIFOs, selectable
transmit and receive FIFO trigger levels, automatic
hardware and software flow control, and data rates of
up to 16 Mbps at 3.3V, 12.5 Mbps at 2.5V and 7.5
Mbps at 1.8V with 4X data sampling rate.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection
increases the performance by simplifying the
software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. Power consumption of the
M670 can be minimized by enabling the sleep mode
and PowerSave mode.
The M670 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M670 is available in 24-pin
QFN, 32-pin QFN and 25-pin BGA packages. All
three packages offer the 16 mode (Intel bus) interface
only.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
Pin-to-pin compatible with XR16L570 in 24-QFN
and 32-QFN packages
•
Intel data bus Interface
•
16 Mbps maximum data rate
•
Selectable TX/RX FIFO Trigger Levels
•
TX/RX FIFO Level Counters
•
Independent TX/RX Baud Rate Generator
•
Fractional Baud Rate Generator
•
Auto RTS/CTS Hardware Flow Control
•
Auto XON/XOFF Software Flow Control
•
Auto RS-485 Half-Duplex Direction Control
•
Multidrop mode w/ Auto Address Detect
•
Sleep Mode with Automatic Wake-up
•
PowerSave mode in 24-pin QFN package
•
Infrared (IrDA 1.0 and 1.1) mode
•
1.62V to 3.63V supply operation
•
Crystal oscillator or external clock input
APPLICATIONS
•
Personal Digital Assistants (PDA)
•
Cellular Phones/Data Devices
•
Battery-Operated Devices
•
Global Positioning System (GPS)
•
Bluetooth
F
IGURE
1. XR16M670 B
LOCK
D
IAGRAM
P w rS ave
A 2:A 0
D 7:D 0
IO R #
IO W #
C S#
IN T
R ES E T
U AR T
R egs
UART
32 B yte TX FIFO
TX &
RX
IR
E N D EC
VCC
(1.62 to 3.63 V )
GND
TX, R X ,
R TS #, C TS #,
D TR #, D S R #,
R I#, C D #
Intel
D ata B us
Interface
BRG
32 B yte R X FIFO
C rystal O sc/Buffer
X TA L1
X TA L2
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16M670
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
F
OR
24-
PIN
QFN, 32-
PIN
QFN
AND
25-BGA P
ACKAGES
REV. 1.0.0
RESET
DTR#
CTS#
Reset
CTS#
RTS#
RTS#
INT
A0
INT
A0
A1
24 23 22 21 20 19 18 17
18 17 16 15 14 13
VCC 19
12
D0 20
11
D1 21
D2 22
D3 23
D4 24
1
D5
2
D6
3
D7
4
RX
5
TX
24-pin QFN
10
9
8
7
6
CS#
A2
IOR#
GND
IOW#
CLK
PwrSave
DSR#
CD#
RI#
VCC
D0
D1
D2
D3
25
26
27
28
29
30
31
32
D4
32-pin QFN
1 2 3 4 5 6 7 8
NC
D5
D6
D7
RX
TX
CS
A1 Corner
1 2
A
B
C
D
E
Transparent Top View
CTS#
VCC
D0
D3
D4
RESET
DTR#
D6
D1
D2
INT
RTS#
D7
TX
D5
A1
A0
DSR#
CS#
RX
A2
IOR#
IOW#
XTAL1
GND
3 4
5
ORDERING INFORMATION
P
ART
N
UMBER
XR16M670IL24
XR16M670IL32
XR16M670IB25
P
ACKAGE
24-Pin QFN
32-Pin QFN
25-Pin BGA
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
2
A1
A2
16 NC
15 NC
14 IOR #
13 GND
12 IOW #
11 XTAL 2
10 XTAL 1
9 NC
XR16M670
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
PIN DESCRIPTIONS
Pin Description
N
AME
24-QFN
P
IN
#
32-QFN
P
IN
#
25-BGA
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
12
13
14
3
2
1
24
23
22
21
20
11
17
18
19
5
4
3
1
32
31
30
29
14
A5
A4
B4
C3
C2
E3
E1
D1
E2
D2
C1
B5
I
Address lines [2:0]. These 3 address lines select the internal regis-
ters in UART during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
This input is read strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal reg-
ister pointed by the address lines [A2:A0], puts the data byte on the
data bus to allow the host processor to read it on the rising edge.
This input is write strobe (active low). The falling edge instigates the
internal write cycle and the rising edge transfers the data byte on
the data bus to an internal register pointed by the address lines.
This input is chip select (active low) to enable the device.
IOW#
9
12
C5
I
CS#
INT
6
15
8
20
D4
A3
I
O
This output is the active high device interrupt output. The output
(OD) state is defined by the user through the software setting of MCR[3].
INT is set to the active mode when MCR[3] is set to a logic 1. INT is
set to the three state mode when MCR[3] is set to a logic 0. See
MCR[3].
MODEM OR SERIAL I/O INTERFACE
TX
5
7
D3
O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6].
UART Clear-to-Send (active low) or general purpose input. It can
be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7].
This input should be connected to VCC when not used.
UART Data-Terminal-Ready (active low) or general purpose output.
RX
4
6
E4
I
RTS#
16
21
B3
O
CTS#
18
24
A1
I
DTR#
-
22
B2
O
3
XR16M670
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
Pin Description
N
AME
DSR#
CD#
RI#
24-QFN
P
IN
#
-
-
-
32-QFN
P
IN
#
25
26
27
25-BGA
P
IN
#
C4
-
-
T
YPE
I
I
I
D
ESCRIPTION
UART Data-Set-Ready (active low) or general purpose input. This
input should be connected to VCC when not used.
UART Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used.
UART Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used.
REV. 1.0.0
ANCILLARY SIGNALS
XTAL1
XTAL2
PwrSave
8
-
7
10
11
-
D5
-
-
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Power-Save (active high). This feature isolates the M670’s data bus
interface from the host preventing other bus activities that cause
higher power drain during sleep mode. See Sleep Mode with Auto
Wake-up and Power-Save Feature section for details. This pin does
not have a pull-down resistor. This input should be connected to
GND when not used.
This input is active high. A 40 ns minimum active pulse on this pin
will reset the internal registers and all outputs of the UART. The
UART transmitter output will be held at logic 1, the receiver input
will be ignored and outputs are reset during reset period (see UART
Reset Conditions).
1.62V to 3.63V power supply.
Power supply common, ground.
The center pad on the backside of the QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on
the PCB should be the approximate size of this center pad and
should be solder mask defined. The solder mask opening should be
at least 0.0025" inwards from the edge of the PCB thermal pad.
No Connects.
RESET
17
23
A2
I
VCC
GND
GND
19
10
Center
Pad
28
13
Center
Pad
B1
E5
-
Pwr
Pwr
Pwr
NC
-
2, 9, 15,
16
-
-
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
4
XR16M670
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR16M670 (M670) is a high performance single channel UART. The configuration registers set is 16550
UART compatible for control, status and data transfer. Additionally, the M670 channel has 32 bytes of transmit
and receive FIFOs, Automatic RTS/CTS Hardware Flow Control, Automatic Xon/Xoff and Special Character
Software Flow Control, infrared encoder and decoder (IrDA ver 1.0 and 1.1), programmable fractional baud
rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 Mbps. The XR16M670 can operate
from 1.62 to 3.63 volts. The M670 is fabricated with an advanced CMOS process.
Larger FIFO
The M670 provides a solution that supports 32 bytes of transmit and receive FIFO memory, instead of 16 bytes
in the XR16L580. The M670 is designed to work with high performance data communication systems, that
requires fast data processing time. Increased performance is realized in the M670 by the larger transmit and
receive FIFOs, FIFO trigger level control and automatic flow control mechanism. This allows the external
processor to handle more networking tasks within a given time. For example, the XR16L580 with a 16 byte
FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including
start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms
intervals. However with the 32 byte FIFO in the M670, the data buffer will not require unloading/loading for 6.1
ms. This increases the service interval giving the external CPU additional time for other applications and
reducing the overall UART interrupt servicing time. In addition, the selectable FIFO level trigger interrupt and
automatic hardware/software flow control is uniquely provided for maximum data throughput performance
especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s
bandwidth requirement, increases performance, and reduces power consumption.
Data Rate
The M670 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate. The device can
operate at 3.3V with a 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 64 MHz on
XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler
bit and sampling rate for data rates of up to 3.68 Mbps.
Enhanced Features
The rich feature set of the M670 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder,
modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility for turning
off (Xon) software flow control with any incoming (RX) character. The M670 includes new features such as 9-
bit (Multidrop) mode, auto RS-485 half-duplex direction control, different baud rate for TX and RX, fast IR mode
and fractional baud rate generator.
5
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