INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT154
4-to-16 line decoder/demultiplexer
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer
FEATURES
•
16-line demultiplexing capability
•
Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
•
2-input enable gate for strobing or expansion
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT154 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT154
The 74HC/HCT154 decoders accept four active HIGH
binary address inputs and provide 16 mutually exclusive
active LOW outputs.
The 2-input enable gate can be used to strobe the decoder
to eliminate the normal decoding “glitches” on the outputs,
or it can be used for the expansion of the decoder.
The enable gate has two AND’ed inputs which must be
LOW to enable the outputs.
The “154” can be used as a 1-to-16 demultiplexer by using
one of the enable inputs as the multiplexed data input.
When the other enable is LOW, the addressed output will
follow the state of the applied data.
TYPICAL
SYMBOL
t
PHL/
t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay A
n
, E
n
to Y
n
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
11
3.5
60
HCT
13
3.5
60
ns
pF
pF
UNIT
September 1993
2
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer
PIN DESCRIPTION
PIN NO.
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17
18, 19
12
23, 22, 21, 20
24
SYMBOL
Y
0
to Y
15
E
0
, E
1
GND
A
0
to A
3
V
CC
74HC/HCT154
NAME AND FUNCTION
outputs (active LOW)
enable inputs (active LOW)
ground (0 V)
address inputs
positive supply voltage
(a)
(b)
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
A
n
to Y
n
propagation delay
E
n
to Y
n
output transition time
+25
typ.
36
13
10
39
14
11
19
7
6
max.
150
30
26
150
30
26
75
15
13
−40
to
+85
min.
max.
190
38
33
190
38
33
95
19
16
−40
to
+125
min.
max.
225
45
38
225
45
38
110
22
19
ns
74HC/HCT154
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
THL
/ t
TLH
ns
Figs 6 and 7
September 1993
5
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